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general description the MAX1987/max1988 are dual-phase, quick-pwm, step-down controllers for imvp-iv cpu core supplies. dual-phase operation reduces input ripple current requirements and output voltage ripple, while easing component selection and layout difficulties. the quick- pwm control scheme provides instantaneous response to fast load-current steps. the MAX1987/max1988 include active voltage positioning with adjustable gain and offset, reducing power dissipation and bulk output capacitance requirements. the MAX1987/max1988 are intended for two different notebook cpu core applications: stepping down the battery directly or stepping down the 5v system supply to create the core voltage. the single-stage conversion method allows these devices to directly step down high- voltage batteries for the highest possible efficiency. alternatively, two-stage conversion (stepping down the 5v system supply instead of the battery) at higher switching frequency provides the minimum possible physical size. the MAX1987/max1988 meet the imvp-iv specifica- tions and can directly interface with the cpu power- good signals from the v ccp and v ccmch rails within the system. the switching regulator features power-up sequencing, automatically ramping up to the intel- specified boot voltage. the MAX1987/max1988 also feature independent four-level logic inputs for setting the boot voltage (b0 to b2) and the suspend voltage (s0 to s2). the MAX1987/max1988 include output undervoltage protection, thermal protection, and system power-ok (syspok) input. when any of these protection features detect a fault, the controller shuts down. additionally, the MAX1987 includes overvoltage protection. the MAX1987/max1988 are available in a low-profile 48-pin 7mm ? 7mm thin qfn package. applications imvp-iv notebook computers multiphase cpu core supply voltage-positioned step-down converters servers/desktop computers features dual-phase, quick-pwm controllers ?.75% v out accuracy over line, load, and temperature active voltage positioning with adjustable gain and offset 6-bit on-board dac (16mv increments) 0.492v to 1.708v output adjust range selectable 200khz/300khz/550khz switching frequency 2v to 28v battery input voltage range adjustable slew rate control drives large synchronous rectifier mosfets output overvoltage protection (MAX1987 only) undervoltage and thermal fault protection imvp-iv power sequencing and timing selectable boot and suspend voltages low-profile 7mm ? 7mm 48-pin thin qfn package MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies ________________________________________________________________ maxim integrated products 1 ordering information 19-2559; rev 0; 7/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. typical operating circuit appears at end of data sheet. part temp range pin-package MAX1987 etm -40 c to +100 c 48 thin qfn 7mm ? 7mm max1988 etm -40 c to +100 c 48 thin qfn 7mm ? 7mm v dd dlm lxm bstm d1 d2 d3 d5 d4 d0 dhm b0 b1 b2 s0 s1 s2 v cc ref ilim ton time 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 cci fb oain- oain+ psi imvpok sysok neg pos ccv gnd csn cmn cmp sus v+ bsts lxs dhs pgnd dls csp 7mm x 7mm thin qfn MAX1987 max1988 top view 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 shdn clken dd0 dpslp pin configuration quick-pwm is a trademark of maxim integrated products, inc. imvp-iv is a trademark of intel corp. confidential information?estricted to intel imvp licensees preliminary www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (circuit of figure1, v+ = 15v, v cc = v dd = v shdn = v ton = v dpslp = v psi = v b1 = v oain- = 5v, v b2 = 2v, v fb = v cmp = v cmn = v csp = v csn = v oain+ = v neg = v pos = 1.26v, v d4 = v d3 = v d2 = 1.0v, v sus = v d5 = v d1 = v d0 = v s0 = v s1 = v s2 = v b0 = 0, t a = 0? to +85? , unless otherwise specified.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to gnd ..............................................................-0.3v to +30v v cc to gnd ..............................................................-0.3v to +6v v dd to pgnd............................................................-0.3v to +6v psi , sus, imvpok, clken , dpslp , sysok, d0 d5 to gnd........................................-0.3v to +6v ilim, fb, pos, neg, ccv, cci, ref, oain+, oain- to gnd.........................................-0.3v to (v cc + 0.3v) cmp, csp, cmn, csn to gnd ..................-0.3v to (v cc + 0.3v) ddo , ton, time, b0, b1, b2, s0, s1, s2 to gnd ..................................-0.3v to (v cc + 0.3v) shdn to gnd (note 1)...........................................-0.3v to +18v dlm, dls to pgnd ....................................-0.3v to (v dd + 0.3v) bstm, bsts to gnd ..............................................-0.3v to +36v dhm to lxm ...........................................-0.3v to (v bstm + 0.3v) lxm to bstm............................................................-6v to +0.3v dhs to lxs..............................................-0.3v to (v bsts + 0.3v) lxs to bsts .............................................................-6v to +0.3v gnd to pgnd .......................................................-0.3v to +0.3v ref short-circuit duration (t a = +70 c) ...................continuous continuous power dissipation 48-pin qfn (derate 26.3mw/ c above +70 c) ...........2.105w operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c note 1: shdn may be forced to 12v, for the purpose of debugging prototype boards using the no-fault test mode, which disables fault protection and disables overlapping operation. parameter symbol conditions min typ max units pwm controller battery voltage, v+ 2 28 input-voltage range v cc , v dd 4.5 5.5 v dac codes from 1.276v to 1.708v -0.75 +0.75 dac codes from 0.844v to 1.260v -1.25 +1.25 dc output-voltage accuracy (note 2) v+ = 4.5v to 28v, includes load regulation error dac codes from 0.492v to 0.828v -3.00 +3.00 % line regulation error v cc = 4.5v to 5.5v, v+ = 4.5v to 28v 5 mv i fb fb -2 +2 input bias current i pos , i neg pos, neg -0.2 +0.2 a pos, neg common-mode range dpslp = gnd 0 2 v pos, neg differential range v pos - v neg , dpslp = gnd -200 +200 mv pos, neg offset gain a os ? v fb /(v pos - v neg ), (v pos - v neg ) = 100mv, dpslp = gnd 0.95 1.00 1.05 mv/mv pos, neg enable time t os measured from the time dpslp goes low to the time in which pos, neg affect a change in the set point (v dac ) 0.1 s 640khz nominal, r time = 23.5k ? ? ? 58 64 70 khz confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure1, v+ = 15v, v cc = v dd = v shdn = v ton = v dpslp = v psi = v b1 = v oain- = 5v, v b2 = 2v, v fb = v cmp = v cmn = v csp = v csn = v oain+ = v neg = v pos = 1.26v, v d4 = v d3 = v d2 = 1.0v, v sus = v d5 = v d1 = v d0 = v s0 = v s1 = v s2 = v b0 = 0, t a = 0 c to +85 c , unless otherwise specified.) parameter symbol conditions min typ max units ton = ref (550khz) 155 180 205 ton = open (300khz) 320 355 390 on-time (note 3) t on v+ = 12v, v fb = v cci = 1.2v ton = v cc (200khz) 475 525 575 ns ton = ref (550khz) 330 375 minimum off-time (note 3) t off ( min ) ton = v cc or open (200khz or 300khz) 435 500 ns ddo delay time t ddo measured from the time fb reaches the voltage set by s0 to s2. clock speed set by r time . 32 clks skip delay time t skip measured from the time when ddo is asserted to the time in which the controller begins pulse-skipping operation 30 clks bias and reference quiescent supply current (v cc )i cc measured at v cc , fb forced above the regulation point 1.70 2.70 ma quiescent supply current (v dd )i dd measured at v dd , fb forced above the regulation point <1 5 a quiescent battery supply current (v+) i v+ measured at v+ 25 50 a shutdown supply current (v cc ) measured at v cc , shdn = gnd 2 5 a shutdown supply current (v dd ) measured at v dd , shdn = gnd <1 5 a shutdown battery supply current (v+) measured at v+, shdn = gnd, v cc = v dd = 0 or 5v <1 5 a reference voltage v ref v cc = 4.5v to 5.5v, i ref = 0 1.990 2.000 2.010 v reference load regulation ? v ref i ref = -10a to +100a -10 +10 mv fault protection output overvoltage protection threshold (MAX1987 only) v ovp measured at fb 1.95 2.00 2.05 v output overvoltage propagation delay (MAX1987 only) t ovp fb forced above 2.05v 10 s output undervoltage protection threshold v uvlo measured at fb with respect to unloaded output voltage 67 70 73 % output undervoltage propagation delay t uvp fb forced 2% below trip threshold 10 s confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure1, v+ = 15v, v cc = v dd = v shdn = v ton = v dpslp = v psi = v b1 = v oain- = 5v, v b2 = 2v, v fb = v cmp = v cmn = v csp = v csn = v oain+ = v neg = v pos = 1.26v, v d4 = v d3 = v d2 = 1.0v, v sus = v d5 = v d1 = v d0 = v s0 = v s1 = v s2 = v b0 = 0, t a = 0 c to +85 c , unless otherwise specified.) parameter symbol conditions min typ max units lower threshold (undervoltage) -13 -10 -7 imvpok, clken threshold v syspok = 5v; measured at fb with respect to unloaded output voltage upper threshold (overvoltage) +7 +10 +13 % clken delay t clken fb in regulation, measured from the rising edge of syspok 30 50 90 s output fault, imvpok, and clken transition blanking time t blank measured from the time when fb reaches the voltage set by the dac code, clock speed set by r time (note 4) 32 clks imvpok delay t imvpok fb in regulation, measured from the falling edge of clken 357ms imvpok, clken output low voltage i sink = 3ma 0.3 v imvpok, clken leakage current high state, imvpok, clken forced to 5.5v 1a v cc undervoltage lockout threshold v uvlo (vcc) rising edge, hysteresis = 90mv, pwm disabled below this level 4.0 4.2 4.4 v thermal shutdown threshold t shdn hysteresis = 15 c 160 c current limit and balance current-limit threshold voltage (positive, default) v limit cmp - cmn, csp - csn; ilim = v cc 27 30 33 mv v ilim = 1v 47 50 53 current-limit threshold voltage (positive, adjustable) v limit cmp - cmn, csp - csn v ilim = 1.5v 72 75 78 mv current-limit threshold voltage (negative) v limit (neg) cmp - cmn, csp - csn; ilim = v cc , sus = gnd, and dpslp = psi = v cc -30 -36 -42 mv current-limit threshold voltage (zero-crossing) v zero cmp - cmn, csp - csn; sus = v cc or dpslp = gnd or psi = gnd 1.5 mv cmp, cmn, csp, csn input ranges 02v cmp, cmn, csp, csn input current v csp = v csn = 0 to 5v -2 +2 a ilim input current i ilim v ilim = 0 to 5v 0.1 200 na current-limit default switchover threshold ilim 3 v cc - 1 v cc - 0.4 v current-balance offset v os ( ibal ) (v cmp - v cmn ) - (v csp - v csn ); i cci = 0, -20mv < (v cmp - v cmn ) <+20mv, 0.5v < v cci < 2.8v -2.0 +2.0 mv confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies _______________________________________________________________________________________ 5 electrical characteristics (continued) (circuit of figure1, v+ = 15v, v cc = v dd = v shdn = v ton = v dpslp = v psi = v b1 = v oain- = 5v, v b2 = 2v, v fb = v cmp = v cmn = v csp = v csn = v oain+ = v neg = v pos = 1.26v, v d4 = v d3 = v d2 = 1.0v, v sus = v d5 = v d1 = v d0 = v s0 = v s1 = v s2 = v b0 = 0, t a = 0 c to +85 c , unless otherwise specified.) parameter symbol conditions min typ max units current-balance transconductance g m ( ibal ) 400 s gate drivers dh_ gate-driver on-resistance r on ( dh ) bst_ - lx_ forced to 5v 1.0 4.5 ? high state (pullup) 1.0 4.5 dl_ gate-driver on-resistance r on ( dl ) low state (pulldown) 0.4 2.0 ? dh_ gate-driver source/sink current i dh dh_ forced to 2.5v, bst_ - lx_ forced to 5v 1.6 a dl_ gate-driver sink current i dl ( sink ) dl_ forced to 5v 4 a dl_ gate-driver source current i d l ( s ou rc e ) dl_ forced to 2.5v 1.6 a dl_ rising 35 dead time t dead dh_ rising 26 ns voltage-positioning amplifier input offset voltage v os -1.5 +1.5 mv input bias current i bias oain+, oain- 0.1 200 na op amp disable threshold oain- 3 v cc - 1 v cc - 0.4 v common-mode input-voltage range v cm guaranteed by cmrr test 0 2.5 v common-mode rejection ratio cmrr v oain+ = v oain- = 0 to 2.5v 70 100 db power-supply rejection ratio psrr v cc = 4.5v to 5.5v 75 100 db large-signal voltage gain a oa r l = 1k ? to v cc /2 70 112 db v cc - v fbh 77 300 output-voltage swing (v oain+ - v oain- ) 10mv, r l = 1k ? to v cc /2 v fbl 47 200 mv input capacitance 11 pf gain-bandwidth product 3 mhz slew rate 0.3 v/s capacitive load stability no sustained oscillations 400 pf logic and i/o logic-input high voltage v ih sus, dpslp , shdn , syspok 2.4 v logic-input low voltage v il sus, dpslp , shdn , syspok 0.8 v logic-input current sus, dpslp , shdn , syspok -1 +1 a confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 6 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure1, v+ = 15v, v cc = v dd = v shdn = v ton = v dpslp = v psi = v b1 = v oain- = 5v, v b2 = 2v, v fb = v cmp = v cmn = v csp = v csn = v oain+ = v neg = v pos = 1.26v, v d4 = v d3 = v d2 = 1.0v, v sus = v d5 = v d1 = v d0 = v s0 = v s1 = v s2 = v b0 = 0, t a = 0 c to +85 c , unless otherwise specified.) parameter symbol conditions min typ max units shdn no-fault threshold to enable no-fault mode 12 15 v 1v logic-input high voltage d0 d5, psi 0.7 v 1v logic-input low voltage d0 d5, psi 0.3 v dac input current d0 d5, psi -1 +1 a driver disable output high voltage ddo , i load = 1ma 2.4 v driver disable output low voltage ddo , i load = 1ma 0.3 v high v cc - 0.4 open 3.15 3.85 ref 1.65 2.35 four-level input logic levels ton, s0 to s2, b0 to b2 low 0.5 v four-level input current ton, s0 to s2, b0 to b2 forced to gnd or v cc -4 +4 a electrical characteristics (circuit of figure 1, v+ = 15v, v cc = v dd = v shdn = v ton = v dpslp = v psi = v b1 = v oain- = 5v, v b2 = 2v, v fb = v cmp = v cmn = v csp = v csn = v oain+ = v neg = v pos = 1.26v, v d4 = v d3 = v d2 = 1.0v, v sus = v d5 = v d1 = v d0 = v s0 = v s1 = v s2 = v b0 = 0, t a = -40 c to +100 c , unless otherwise specified.) (note 5) parameter symbol conditions min max units pwm controller battery voltage, v+ 2 28 input-voltage range v cc , v dd 4.5 5.5 v dac codes from 1.276v to 1.708v -1.00 +1.00 dac codes from 0.844v to 1.260v -1.50 +1.50 dc output-voltage accuracy (note 2) v+ = 4.5v to 28v, includes load regulation error dac codes from 0.492v to 0.828v -3.5 +3.5 % pos, neg offset gain a off ? v fb /(v pos - v neg ), (v pos - v neg ) = 100mv, dpslp = gnd 0.95 1.05 mv/mv 640khz nominal, r time = 23.5k ? ? ? 58 70 khz ton = ref (550khz) 155 205 ton = open (300khz) 320 390 on-time (note 3) t on v+ = 12v, v fb = v cci = 1.2v ton = v cc (200khz) 475 575 ns confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies _______________________________________________________________________________________ 7 electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v cc = v dd = v shdn = v ton = v dpslp = v psi = v b1 = v oain- = 5v, v b2 = 2v, v fb = v cmp = v cmn = v csp = v csn = v oain+ = v neg = v pos = 1.26v, v d4 = v d3 = v d2 = 1.0v, v sus = v d5 = v d1 = v d0 = v s0 = v s1 = v s2 = v b0 = 0, t a = -40 c to +100 c , unless otherwise specified.) (note 5) parameter symbol conditions min max units ton = ref (550khz) 375 minimum off-time (note 3) t off ( min ) ton = v cc or open (200khz or 300khz) 500 ns bias and reference quiescent supply current (v cc )i cc measured at v cc , fb forced above the regulation point 3.00 ma quiescent supply current (v dd )i dd measured at v dd , fb forced above the regulation point 30 a quiescent battery supply current (v+) i v+ measured at v+ 50 a shutdown supply current (v cc ) measured at v cc , shdn = gnd 20 a shutdown supply current (v dd ) measured at v dd , shdn = gnd 20 a shutdown battery supply current (v+) measured at v+, shdn = gnd, v cc = v dd = 0 or 5v 20 a reference voltage v ref v cc = 4.5v to 5.5v, i ref = 0 1.985 2.015 v fault protection output overvoltage protection threshold (MAX1987 only) measured at fb 1.95 2.05 v output undervoltage protection threshold measured at fb with respect to unloaded output voltage 67 73 % lower threshold (undervoltage) -13 -7 imvpok, clken threshold v syspok = 5v; measured at fb with respect to unloaded output voltage upper threshold (overvoltage) 713 % clken delay t clken fb in regulation, measured from the rising edge of syspok 30 s imvpok delay t imvpok fb in regulation, measured from the falling edge of clken 3ms v cc undervoltage lockout threshold v uvlo (vcc) rising edge, hysteresis = 90mv, pwm disabled below this level 3.95 4.45 v current limit and balance current-limit threshold voltage (positive, default) v limit cmp - cmn, csp - csn; ilim = v cc 25 35 mv v ilim = 1v 45 55 current-limit threshold voltage (positive, adjustable) v limit cmp - cmn, csp - csn v ilim = 1.5v 70 80 mv confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 8 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v cc = v dd = v shdn = v ton = v dpslp = v psi = v b1 = v oain- = 5v, v b2 = 2v, v fb = v cmp = v cmn = v csp = v csn = v oain+ = v neg = v pos = 1.26v, v d4 = v d3 = v d2 = 1.0v, v sus = v d5 = v d1 = v d0 = v s0 = v s1 = v s2 = v b0 = 0, t a = -40 c to +100 c , unless otherwise specified.) (note 5) parameter symbol conditions min max units current-limit threshold voltage (negative) v limit (neg) cmp - cmn, csp - csn; ilim = v cc , sus = gnd and dpslp = v cc -27 -45 mv current-balance offset v os ( ibal ) (v cmp - v cmn ) - (v csp - v csn ); i cci = 0, -20mv < (v cmp - v cmn ) < 20mv, 0.5v < v cci < 2.8v -3 +3 mv gate drivers dh_gate-driver on-resistance r on ( dh ) bst_ - lx_forced to 5v 4.5 ? high state (pullup) 4.5 dl_gate-driver on-resistance r on ( dl ) low state (pulldown) 2.0 ? voltage-positioning amplifier input offset voltage v os -2.5 +2.5 mv common-mode input voltage range v cm guaranteed by cmrr test 0 2.5 v v cc - v fbh 300 output-voltage swing (v oain+ - v oain- ) 10mv, r l = 1k ? to v cc /2 v fbl 200 mv logic and i/o logic-input high voltage v ih sus, dpslp , shdn , syspok 2.4 v logic-input low voltage v il sus, dpslp , shdn , syspok 0.8 v 1v logic-input high voltage d0 d5, psi 0.7 v 1v logic-input low voltage d0 d5, psi 0.3 v high v cc - 0.4 open 3.15 3.85 ref 1.65 2.35 four-level input logic levels ton, s0 to s2, b0 to b2 low 0.5 v note 2: dc output accuracy specifications refer to the trip level of the error amplifier. the output voltage has a dc regulation higher than the trip level by 50% of the output ripple. when pulse-skipping, the output rises by approximately 1.5% when transition- ing from continuous conduction to no load. note 3: on-time and minimum off-time specifications are measured from 50% to 50% at the dhm and dhs pins, with lx_ forced to gnd, bst_ forced to 5v, and a 500pf capacitor from dh_ to lx_ to simulate external mosfet gate capacitance. actual in- circuit times can be different due to mosfet switching speeds. note 4: the output fault-blanking time is measured from the time when fb reaches the regulation voltage set by the dac code. during power-up, the regulation voltage is set by the boot dac code (b0 to b2). during normal operation (sus = gnd), the regulation voltage is set by the vid dac inputs (d0 d5). during suspend mode (sus = v cc ), the regulation voltage is set by the suspend dac inputs (s0 to s2). note 5: specifications to t a = -40 c to +100 c are guaranteed by design and are not production tested. confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies _______________________________________________________________________________________ 9 output voltage vs. load current (v out = 1.356v) MAX1987/88 toc01 load current (a) output voltage (v) 30 20 10 1.20 1.25 1.30 1.35 1.40 1.15 040 efficiency vs. load current (v out = 1.356v) MAX1987/88 toc02 load current (a) efficiency (%) 10 1 60 70 80 90 100 50 0.1 100 v in = 12v v in = 8v v in = 20v psi = gnd psi = v cc output voltage vs. load current (v out = 0.844v) MAX1987/88 toc03 load current (a) output voltage (v) 25 20 15 10 5 0.75 0.78 0.80 0.83 0.85 0.88 0.73 030 efficiency vs. load current (v out = 0.844v) MAX1987/88 toc04 load current (a) efficiency (%) 10 1 60 70 80 90 100 50 0.1 100 v in = 12v v in = 8v v in = 20v psi = gnd psi = v cc output voltage vs. load current (v out = 0.748v) MAX1987/88 toc05 load current (a) output voltage (v) 15 10 5 0.68 0.69 0.70 0.71 0.72 0.73 0.74 0.75 0.76 0.77 0.67 020 sus = v cc efficiency vs. load current (v out = 0.748v) MAX1987/88 toc06 load current (a) efficiency (%) 10 1 60 70 80 90 100 50 0.1 100 v in = 12v v in = 8v v in = 20v psi = gnd psi = v cc -5 -2 -3 -4 0 -1 4 3 2 1 5 -40 -20 0 20 40 60 80 100 reference voltage shift vs. temperature MAX1987/88 toc07 temperature ( c) ? v ref (mv) switching frequency vs. load current MAX1987/88 toc08 load current (a) switching frequency (khz) 30 20 10 100 200 300 400 0 040 forced-pwm (v psi = 5v) skip mode (v psi = 0) 220 240 280 260 300 320 010 5 15202530 switching frequency vs. input voltage MAX1987/88 toc09 input voltage (v) frequency (khz) i out = 20a no load typical operating characteristics (circuit of figure 1, v+ = 12v, v cc = v dd = 5v, sus = gnd, shdn = dpslp = psi = v cc , b0 to b2 set for 1.372v, s0 to s2 set for 0.748v, t a = +25 c, unless otherwise specified.) confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 10 ______________________________________________________________________________________ output offset voltage vs. pos-neg differential voltage MAX1987/88 toc14 pos-neg differential voltage (mv) output offset voltage (mv) 400 200 0 -200 -400 -400 -200 0 200 400 600 -600 -600 600 60 -40 0.1 10 100 1000 1 10,000 voltage-positioning amplifier gain and phase vs. frequency -20 -10 0 -30 MAX1987/88 toc18 frequency (khz) gain (db) phase (degrees) 10 20 30 40 50 180 -180 -108 -72 -36 -144 0 36 72 108 144 gain phase typical operating characteristics (continued) (circuit of figure 1, v+ = 12v, v cc = v dd = 5v, sus = gnd, shdn = dpslp = psi = v cc , b0 to b2 set for 1.372v, s0 to s2 set for 0.748v, t a = +25 c, unless otherwise specified.) 200 240 220 280 260 320 300 340 -40 0 20 -20 40 60 80 100 switching frequency vs. temperature MAX1987/88 toc10 temperature ( c) frequency (khz) no load 20a no load v out = 1.356v 35 36 38 37 39 40 -40 0 -20 20406080100 output current at current limit vs. temperature MAX1987/88 toc11 temperature ( c) maximum load current (a) 0 20 60 40 80 100 010 5 15202530 no load supply current vs. input voltage (forced-pwm mode) MAX1987/88 toc12 input voltage (v) supply current (ma) i cc + i dd i+ psi = v cc 0 0.5 1.5 1.0 2.0 2.5 010 5 15202530 no load supply current vs. input voltage (pulse skipping) MAX1987/88 toc13 input voltage (v) supply current (ma) i cc + i dd i+ psi = gnd 0 10 20 30 40 50 0.834 0.839 0.844 0.849 0.854 0.844v output-voltage distribution MAX1987/88 toc15 output voltage (v) sample percentage (%) 0 5 15 10 20 25 1.995 1.999 1.997 2.001 2.003 2.005 reference voltage distribution MAX1987/88 toc16 reference voltage (v) sample percentage (%) 0 10 5 20 15 25 30 0.98 1.00 0.99 1.01 1.02 pos-neg offset gain distribution MAX1987/88 toc17 pos-neg offset gain sampe percentage (%) confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies ______________________________________________________________________________________ 11 vps amplifier offset voltage vs. common-mode voltage MAX1987/88 toc19 common-mode voltage (v) offset voltage ( v) 4 3 2 1 20 40 60 80 100 120 140 160 180 0 05 vps amplifier disabled power-up sequence MAX1987/88 toc21 100 s/div 0 a b c d 5v 0 5v 0 0 5v boot vid a. v shdn = 0 to 5v, 5v/div b. v out = 0 to 1.372v to 0.844v, 500mv/div c. clken, 5v/div d. ddo, 5v/div r load = 80m ? soft-start MAX1987/88 toc22 100 s/div 0 a b c d 5v 0 10a 0 0 boot vid a. v shdn = 0 to 5v, 5v/div b. v out = 0 to 1.372v to 0.844v, 500mv/div c. i lm , 10a/div d. i ls , 10a/div r load = 80m ? system power-ok MAX1987/88 toc23 20 s/div 0 a b c d 5v 0 5v boot (1.372v) high freq vid (1.356v) low freq vid (0.844v) a. v syspok = 0 to 5v, 5v/div b. high freq: v out = 1.356v, 200mv/div c. low freq: v out = 0.844v, 200mv/div d. clken, 5v/div imvpok delay MAX1987/88 toc24 1ms/div 0 0 a b c d 5v 0 0 5v 5v boot (1.372v) a. v shdn = 0 to 5v, 5v/div b. v out = 0 to 0.844v, 1v/div c. clken, 5v/div d. imvpok, 5v/div typical operating characteristics (continued) (circuit of figure 1, v+ = 12v, v cc = v dd = 5v, sus = gnd, shdn = dpslp = psi = v cc , b0 to b2 set for 1.372v, s0 to s2 set for 0.748v, t a = +25 c, unless otherwise specified.) 0 0.2 0.6 0.4 0.8 1.0 inductor current difference vs. load current MAX1987/88 toc20 load current (a) i l(cs) - i l(cm) (a) 020 10 30 40 psi = gnd psi = v cc confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 12 ______________________________________________________________________________________ shutdown sequence MAX1987/88 toc25 40 s/div 0 0.84v 0 0 a b c d e 5v 5v 0 5v 0 5v a. v shdn = 5v to 0, 5v/div b. v out = 0.844v to 0, 500mv/div c. clken, 5v/div d. imvpok, 5v/div e. ddo, 5v/div r load = 80m ? soft shutdown MAX1987/88 toc26 40 s/div 0 0.84v 0 a b c d 5v 0 0 a. v shdn = 5v to 0, 5v/div b. v out = 0.844v to 0, 500mv/div c. i lm , 10a/div d. i ls , 10a/div r load = 80m ? load transient (v out = 1.356v) MAX1987/88 toc27 40 s/div 0 1.356v a b c d 25a 0 0 a. i out = 0 to 25a, 20a/div b. v out = 1.356v to 1.281v, 50mv/div c. i lm , 10a/div d. i ls , 10a/div load transient (v out = 0.844v) MAX1987/88 toc28 40 s/div 0 0.844v a b c d 10a 0 0 a. i out = 0 to 10a, 10a/div b. v out = 0.844v to 0.814v, 20mv/div c. i lm , 10a/div d. i ls , 10a/div entering deep-sleep mode MAX1987/88 toc29 20 s/div 0 1.350v 1.318v a b c d 5v 0 0 a. v dpslp = 5v to 0, 5v/div b. v out = 1.350v to 1.318v, 50mv/div c. lxm, 10v/div d. lxs, 10v/div sus = gnd, i out = 1a exiting deep-sleep mode MAX1987/88 toc30 20 s/div 0 1.351v 1.318v a b c d 5v 0 0 a. v dpslp = 0 to 5v, 5v/div b. v out = 1.318v to 1.351v, 50mv/div c. lxm, 10v/div d. lxs, 10v/div sus = gnd, i out = 1a typical operating characteristics (continued) (circuit of figure 1, v+ = 12v, v cc = v dd = 5v, sus = gnd, shdn = dpslp = psi = v cc , b0 to b2 set for 1.372v, s0 to s2 set for 0.748v, t a = +25 c, unless otherwise specified.) confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies ______________________________________________________________________________________ 13 deep-sleep transition MAX1987/88 toc31 40 s/div 0 1.350v 1.318v a b c d 5v 0 0 a. v dpslp = 5v to 0, 5v/div b. v out = 1.350v to 1.318v, 50mv/div c. i lm , 10a/div d. i ls , 10a/div sus = gnd, i out = 1a entering suspend mode MAX1987/88 toc32 40 s/div 0 0.751v 1.318v a b c d 5v 0 0 a. v sus = 0 to 5v, 5v/div b. v out = 1.318v to 0.751v, 500mv/div c. lxm, 10v/div d. lxs, 10v/div dpslp = gnd, i out = 1.0a exiting suspend mode MAX1987/88 toc33 40 s/div 0 0.751v 1.318v a b c d 5v 0 0 a. v sus = 5v to 0, 5v/div b. v out = 0.751v to 1.318v, 500mv/div c. lxm, 10v/div d. lxs, 10v/div dpslp = gnd, i out = 1a suspend transition MAX1987/88 toc34 100 s/div 0 0.751v 1.318v a b c d 5v 0 0 a. v sus = 0 to 5v, 5v/div b. v out = 1.318v to 0.751v, 500mv/div c. i lm , 10a/div d. i ls , 10a/div dpslp = gnd, i out = 1a MAX1987/88 toc35 20 s/div 0 1.356v a b c d 5v 0 0 a. v psi = 5v to 0, 5v/div b. v out = 1.356v, 50mv/div c. lxm, 10v/div d. lxs, 10v/div i out = 1a psi transition typical operating characteristics (continued) (circuit of figure 1, v+ = 12v, v cc = v dd = 5v, sus = gnd, shdn = dpslp = psi = v cc , b0 to b2 set for 1.372v, s0 to s2 set for 0.748v, t a = +25 c, unless otherwise specified.) confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 14 ______________________________________________________________________________________ pin description MAX1987/88 toc37 20 s/div 0 1.356v 1.228v a b c d 1v 0 0 a. v d3 = 0 to 1v, 1v/div b. v out = 1.356v to 1.228v, 100mv/div c. i lm , 10a/div d. i ls , 10a/div dynamic vid transition (d3 = 128mv) typical operating characteristics (continued) (circuit of figure 1, v+ = 12v, v cc = v dd = 5v, sus = gnd, shdn = dpslp = psi = v cc , b0 to b2 set for 1.372v, s0 to s2 set for 0.748v, t a = +25 c, unless otherwise specified.) MAX1987/88 toc36 20 s/div 0 1.356v 1.340v a b c d 1v 0 0 a. v d0 = 0 to 1v, 1v/div b. v out = 1.356v to 1.340v, 20mv/div c. i lm , 10a/div d. i ls , 10a/div dynamic vid transition (d0 = 16mv) pin name function 1time slew-rate adjustment pin. connect a resistor from time to gnd to set the internal slew-rate clock. a 235k ? to 23.5k ? resistor sets the clock from 64khz to 640khz, f slew = 320khz 47k ? /r time . 2ton on-time selection control input. this four-level input sets the k-factor value (table 3) used to determine the dh on-time (see the on-time one-shot section): gnd = 1000khz (untested), ref = 550khz, open = 300khz, v cc = 200khz per phase 3, 4, 5 b0, b1, b2 boot-mode voltage select inputs. b0 to b2 are four-level digital inputs that select the boot-mode vid code (table 6) for the boot-mode multiplexer inputs. during power-up, the boot-mode vid code is delivered to the dac (see the internal multiplexers section). 6, 7, 8 s0, s1, s2 suspend-mode voltage select inputs. s0 to s2 are four-level digital inputs that select the suspend-mode vid code (table 5) for the suspend-mode multiplexer inputs. if sus is high, the suspend-mode vid code is delivered to the dac (see the internal multiplexers section), overriding any other voltage setting (figure 9). 9 shdn shutdown control input. this input cannot withstand the battery voltage. connect to v cc for normal operation. connect to ground to put the ic into its 1a shutdown state. during the transition from normal operation to shutdown, the output voltage is ramped down at the output voltage slew rate programmed by the time pin. in shutdown mode, dlm and dls are forced to v dd to clamp the output to ground. forcing shdn to 12v~15v disables both overvoltage protection and undervoltage protection circuits, disables overlap operation, and clears the fault latch. do not connect shdn to >15v. 10 ref 2v reference output. bypass to gnd with a 0.22f or greater ceramic capacitor. the reference can source 100a for external loads. loading ref degrades output-voltage accuracy according to the ref load regulation error. 11 ilim current-limit adjustment. the current-limit threshold defaults to 30mv if ilim is connected to v cc . in adjustable mode, the current-limit threshold voltage is precisely 1/20th the voltage seen at ilim over a 200mv to 1.5v range. the logic threshold for switchover to the 30mv default value is approximately v cc - 1v. confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies ______________________________________________________________________________________ 15 pin description (continued) pin name function 12 v cc analog supply voltage input for pwm core. connect v cc to the system supply voltage (4.5v to 5.5v) with a series 10 ? resistor. bypass to gnd with a 1f or greater ceramic capacitor, as close to the ic as possible. 13 gnd analog ground. connect the MAX1987/max1988s exposed pad to analog ground. 14 ccv voltage integrator capacitor connection. connect a 47pf to 1000pf (270pf typ) capacitor from ccv to analog ground (gnd) to set the integration time constant. 15 pos feedback offset adjust positive input. the output shifts by 100% (typ) of the differential input voltage appearing between pos and neg when dpslp is low. the common-mode range of pos and neg is 0 to 2v. pos and neg should be generated from resistor-dividers from the output. 16 neg feedback offset adjust negative input. the output shifts by 100% (typ) of differential input voltage appearing between pos and neg when dpslp is low. the common-mode range of pos and neg is 0 to 2v. pos and neg should be generated from resistor-dividers from the output. 17 cci current balance compensation. connect a 470pf capacitor between cci and fb (see the current balance compensation section). an additional 470k ? to 1m ? resistor between cci and fb for low-frequency operation. 18 fb feedback input. fb is internally connected to both the feedback input and the output of the voltage- positioning op amp (figure 2). connect a resistor between fb and oain- (figure 1) to set the voltage- positioning gain (see the setting voltage positioning section). 19 oain- dual-mode op amp inverting input and op amp disable input. when using the internal op amp for additional voltage-positioning gain (figure 1), connect to the negative terminal of the current-sense resistor through a 1.0k ? 1% resistor as described in the setting voltage positioning section. connect oain- to v cc to disable the op amp. the logic threshold to disable the op amp is approximately v cc - 1v. 20 oain+ op amp noninverting input. when using the internal op amp for additional voltage-positioning gain (figure 1), connect to the positive terminal of the current-sense resistor through a resistor as described in the setting voltage positioning section. 21 psi power-status indicator input. when psi is pulled low, the MAX1987/max1988 immediately enter pulse- skipping operation, blank the imvpok output high, and blank the clken output low. 22 syspok system power-good input. primarily, syspok serves as the wired nor junction of the open-drain power- good signals for the v ccp and v ccmch supplies. a falling edge on syspok shuts down the MAX1987/max1988 and sets the fault latch. toggle shdn or cycle v cc power below 1v to restart the controller. 23 imvpok open-drain power-good output. after output voltage transitions, except during power-up and power-down, if out is in regulation, then imvpok is high impedance. imvpok is high impedance whenever the slew rate control is active (output voltage transitions). imvpok is forced low in shutdown. a pullup resistor on imvpok causes additional finite shutdown current. imvpok also reflects the state of syspok and includes a 3ms (min) delay for power-up. 24 clken clock enable logic output. this inverted logic output indicates when syspok is high and the output voltage sensed at fb is in regulation. clken is forced low during vid transitions. 25 30 d5 d0 low-voltage vid dac code inputs. d0 is the lsb, and d5 is the msb of the internal 6-bit vid dac (table 4). the d0 d5 inputs do not have internal pullups. these 1.0v logic inputs are designed to interface directly with the cpu. in all normal active modes (modes other than suspend mode and boot mode), the output voltage is set by the vid code indicated by the d0 d5 logic-level voltages on d0 d5. in suspend mode (sus = high), the decoded state of the four-level s0 to s2 inputs sets the output voltage. in boot mode (see the power-up sequence section), the decoded state of the four-level b0 to b2 inputs set the output voltage. confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 16 ______________________________________________________________________________________ pin description (continued) pin name function 31 ddo driver-disable output. this ttl logic output can be used to disable the driver outputs on slave-switching regulator controllers, such as the max1980 forcing a high-impedance condition and making it possible for the MAX1987/max1988 master controller to operate in low-current skip mode. ddo goes low 32 r time clock cycles after the MAX1987/max1988 complete a transition to the suspend mode or deep-sleep voltage (see the low-power pulse skipping section). another 32 clock cycles later, the MAX1987/max1988 enter automatic pulse-skipping operation. 32 bstm main boost flying capacitor connection. an optional resistor in series with bstm allows the dhm pullup current to be adjusted. 33 lxm main inductor connection. lxm is the internal lower supply rail for the dhm high-side gate driver. 34 dhm main high-side gate-driver output swings lxm to bstm 35 dlm main low-side gate driver output. dlm swings from pgnd to v dd . dlm is forced high after the MAX1987/max1988 power down ( shdn = gnd) or when the MAX1987 detects an overvoltage fault. the max1988 does not include overvoltage protection. 36 v dd supply voltage input for the dlm and dls gate drivers. connect to the system supply voltage (4.5v to 5.5v). bypass v dd to pgnd with a 2.2f or greater ceramic capacitor, as close to the ic as possible. 37 pgnd power ground. ground connection for the low-side gate drivers dlm and dls. 38 dls secondary low-side gate driver output. dls swings from pgnd to v dd . dls is forced high after the MAX1987/max1988 power down ( shdn = gnd) or when the MAX1987 detects an overvoltage fault. the max1988 does not include overvoltage protection. 39 dhs secondary high-side gate-driver output swings lxs to bsts 40 lxs secondary inductor connection. lxs is the internal lower supply rail for the dhs high-side gate driver. 41 bsts secondary boost flying capacitor connection. an optional resistor in series with bsts allows the dhs pullup current to be adjusted. 42 v+ battery voltage sense connection. used only for pwm one-shot timing. dh_ on-time is inversely proportional to input voltage over a range of 2v to 28v. 43 sus suspend-mode control input. when sus is high, the regulator slews to the suspend voltage level. this level is set with four-level logic signals at the s0 to s2 inputs. 32 clock cycles after the transition to the suspend- mode voltage is completed, ddo goes low (see the low-power pulse skipping section). another 32 clock cycles later, the MAX1987/max1988 are allowed to enter pulse-skipping operation. 44 dpslp deep-sleep control input. when dpslp is low, the system enters the deep-sleep state and the regulator applies the appropriate deep-sleep offset. the MAX1987/max1988 add the offset measured at the pos and neg pins to the output. 32 clock cycles after the deep-sleep transition is completed, ddo goes low (see the low-power pulse skipping section). another 32 clock cycles later, the MAX1987/max1988 are allowed to enter pulse-skipping operation. 45 cmp main inductor positive current-sense input 46 cmn main inductor negative current-sense input 47 csn secondary inductor negative current-sense input 48 csp secondary inductor positive current-sense input confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies ______________________________________________________________________________________ 17 table 1. component selection for standard multiphase applications (figure 1) designation component input voltage range* 7v to 24v vid output voltage (d5 d0) 1.356v (d5 d0 = 010110) boot voltage (b0 to b2) 1.372v (b2 = ref, b1 = ref, b0 = ref) suspend voltage (s0 to s2) 0.748v (s2 = v cc , s1 = v cc , s0 = gnd) deep-sleep offset voltage (pos, neg) 2.7% maximum load current (typ) 40a inductor (l m , l s ) 0.6h panasonic etqp1h0r6bfa or sumida cdep134h-0r6 switching frequency 300khz (ton = float) high-side mosfet (n h , per phase) fairchild (2) fds6694 or siliconix (2) si4860dy low-side mosfet (n l , per phase) fairchild (2) fds6688 or siliconix (2) si4362dy input capacitance (c in ) (6) 10f, 25v taiyo yuden tmk432bj106km or tdk c4532x5r1e106m output capacitance (c out ) (3) 470f, 2.5v sanyo 2r5tpd470m or (4) 330f, 2.5v panasonic eefueod33ixr current-sense resistor (r sense , per phase) 1.5m ? panasonic erjm1wtj1m5u * input voltages less than 7v require additional input capacitance. table 2. component suppliers manufacturer phone website bi technologies 714-447-2345 (usa) www.bitechnologies.com central semiconductor 631-435-1110 (usa) www.centralsemi.com coilcraft 800-322-2645 (usa) www.coilcraft.com coiltronics 561-752-5000 (usa) www.coiltronics.com fairchild semiconductor 888-522-5372 (usa) www.fairchildsemi.com international rectifier 310-322-3331 (usa) www.irf.com kemet 408-986-0424 (usa) www.kemet.com panasonic 847-468-5624 (usa) www.panasonic.com sanyo 65-281-3226 (singapore) 408-749-9714 (usa) www.secc.co.jp siliconix (vishay) 203-268-6261 (usa) www.vishay.com sumida 408-982-9660 (usa) www.sumida.com taiyo yuden 03-3667-3408 (japan) 408-573-4150 (usa) www.t-yuden.com tdk 847-803-6100 (usa) 81-3-5201-7241 (japan) www.component.tdk.com toko 858-675-8013 (usa) www.tokoam.com confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 18 ______________________________________________________________________________________ preliminary off on bstm dhm lxm dlm v dd v cc d0 d1 d3 d4 fb dac inputs (1v logic) ref c ref 0.22 f c ccv 270pf pgnd v+ ccv neg cci s0 s1 suspend inputs (four-level logic) pos csp ilim time sus psi mode control c3 100pf r time 28k ? r8 100k ? power ground analog ground gnd d5 s2 b0 b1 boot inputs (four-level logic) b2 oain- oain+ cmn cmp imvpok syspok r12 100k ? r13 100k ? r11 100k ? c2 1 f ton float (300khz) power-good logic signals r2 750 ? r3 1.0k ? c cci 470pf r9 30.1k ? input* 8v to 24v l m c in n h(m) n l(m) r cm c bst(m) 0.1 f r10 10 ? 5v bias supply c1 2.2 f ddo shdn dpslp clken MAX1987 max1988 l s c in n h(s) n l(s) r cs c bst(s) 0.1 f bst diodes r1 1.5k ? r7 100k ? r4 750 ? r5 1.0k ? r6 2.74k ? csn bsts dhs lxs dls r cci 1m ? output c out c out *lower input voltages require addtional input capacitance d2 r14 4.7k ? c4 4.7nf figure 1. standard application circuit (master) confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
detailed description 5v bias supply (v cc and v dd ) the MAX1987/max1988 require an external 5v bias sup- ply in addition to the battery. typically, this 5v bias sup- ply is the notebook s 95% efficient 5v system supply. keeping the bias supply external to the ic improves effi- ciency and eliminates the cost associated with the 5v lin- ear regulator that would otherwise be needed to supply the pwm circuit and gate drivers. if standalone capability is needed, the +5v bias supply can be generated with an external linear regulator. the 5v bias supply must provide v cc (pwm controller) and v dd (gate-drive power), so the maximum current drawn is: i bias = i cc + f sw (q g(low) + q g(high) ) = 10ma to 100ma (typ) where i cc is 1.7ma (typ), f sw is the switching frequency, and q g(low) and q g(high) are the mosfet data sheet s total gate-charge specification limits at v gs = 5v. v+ and v dd can be connected together if the input power source is a fixed 4.5v to 5.5v supply. if the 5v bias supply is powered up prior to the battery supply, the enable signal ( shdn going from low to high) must be delayed until the battery voltage is present to ensure startup. free-running, constant on-time pwm controller with input feedforward the quick-pwm control architecture is a pseudo-fixed- frequency, constant-on-time, current-mode regulator with voltage feedforward (figure 2). this architecture relies on the output filter capacitor s esr to act as the current-sense resistor, so the output ripple voltage pro- vides the pwm ramp signal. the control algorithm is simple: the high-side switch on-time is determined sole- ly by a one-shot whose period is inversely proportional to input voltage, and directly proportional to output volt- age and the difference between the main and sec- ondary inductor currents (see the on-time one-shot section). another one-shot sets a minimum off-time. the on-time one-shot is triggered if the error comparator is low, the low-side switch currents are below the current- limit threshold, and the minimum off-time one-shot has timed out. the controller maintains 180 out-of-phase operation by alternately triggering the main and sec- ondary phases after the error comparator drops below the output voltage set point. on-time one-shot (ton) the core of each phase contains a fast, low-jitter, adjustable one-shot that sets the high-side mosfet s on-time. the one-shot for the main phase simply varies the on-time in response to the input and feedback volt- ages. the main high-side switch on-time is inversely proportional to the input voltage as measured by the v+ input, and proportional to the feedback voltage (v fb ): where k is set by the ton pin-strap connection (table 3) and 0.075v is an approximation to accommodate the expected drop across the low-side mosfet switch. the one-shot for the secondary phase varies the on- time in response to the input voltage and the difference between the main and secondary inductor currents. two identical transconductance amplifiers integrate the difference between the master and slave current-sense signals. the summed output is internally connected to cci, allowing adjustment of the integration time con- stant with a compensation network connected between cci and fb. the resulting compensation current and voltage are determined by the following equations: where z cci is the impedance at the cci output. the secondary on-time one-shot uses this integrated signal (v cci ) to set the secondary high-side mosfets on-time. when the main and secondary current-sense signals (v cm = v cmp - v cmn and v cs = v csp - v csm ) become unbalanced, the transconductance amplifiers adjust the secondary on time, which increases or decreases the secondary inductor current until the cur- rent-sense signals are properly balanced: this algorithm results in a nearly constant switching fre- quency and balanced inductor currents, despite the lack of a fixed-frequency clock generator. the benefits of a constant switching frequency are twofold: first, the tk vv v k vv v k iz v main on time secondary current balance correction on nd cci in fb in cci cci in () . . ( ) ( ) 2 0 075 0 075 = + ? ? ? ? ? ? = + ? ? ? ? ? ? + ? ? ? ? ? ? =+ ? igv v gvv vviz cci m cmp cmn m csp csn cci fb cci cci = =+ ?? ? ()() t kv v v on main fb in () (.) = + 0 075 MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies ______________________________________________________________________________________ 19 preliminary confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
MAX1987/max1988 frequency can be selected to avoid noise-sensitive regions such as the 455khz if band; second, the inductor ripple-current operating point remains relative- ly constant, resulting in easy design methodology and predictable output-voltage ripple. the on-time one- shots have good accuracy at the operating points specified in the electrical characteristics (10% at 200khz and 300khz, 12% at 550khz). on-times at operating points far removed from the conditions speci- fied in the electrical characteristics can vary over a wider range. for example, the 550khz setting typically runs about 10% slower with inputs much greater than 12v due to the very short on-times required. on-times translate only roughly to switching frequencies. the on-times guaranteed in the electrical characteristics are influenced by switching delays in the external high- side mosfet. r esistive losses, including the inductor, both mosfets, output capacitor esr, and pc board copper losses in the output and ground tend to raise the switching frequency at higher output currents. also, the dead-time effect increases the effective on-time, reducing the switching frequency. it occurs only in pwm mode (sus = low, dpslp = low) and during dynamic output voltage transitions when the inductor current reverses at light or negative load currents. with reversed inductor current, the inductor s emf causes lx to go high earlier than normal, extending the on-time by a period equal to the dh-rising dead time. for loads above the critical conduction point, where the dead- time effect is no longer a factor, the actual switching frequency (per phase) is: where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pc board resistances; v drop2 is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and pc board resistances; and t on is the on-time as deter- mined above. current balance without active current-balance circuitry, the current matching between phases depends on the mosfets on-resistance (r ds(on) ), thermal ballasting, on-/off-time matching, and inductance matching. for example, vari- ation in the low-side mosfet on-resistance (ignoring thermal effects) results in a current mismatch that is proportional to the on-resistance difference: thermal ballasting as the loaded mosfets heat up actually improves the current balance. the stronger mosfet (the phase with the lower r ds(on) ) pulls more current, which heats up the mosfet more than the other phase, increasing the thereby reducing the current mismatch. taking thermal effects into account, the on- resistance of the switching mosfets can be determined by the following equation: where r ta(25) is the on-resistance at room temperature, i l is the inductor current through the mosfet, r ja ( c/w) is the junction-to-ambient thermal resistance of the mosfet package, and ? r tempco (0.5%/ c) is the temperature coefficient of the mosfet. thermal ballast- ing can typically reduce the current mismatch by as much as a third. unfortunately, mismatches between on- times, off-times, and inductor values increase the worst- case current imbalance making it impossible to passively guarantee accurate current balancing. the MAX1987/max1988 integrate the difference between the current-sense voltages and adjusts the on- time of the secondary phase to maintain current bal- ance. the current balance now relies on the accuracy of the current-sense resistors instead of the inaccurate, thermally sensitive on-resistance of the low-side tracking mosfets. with active current balancing, the current mismatch is simply determined by the current-sense resistor values and the offset voltage of the transconduc- tance amplifiers: where r sense = r cm = r cs and v os(ibal) is the current -balance offset specification in the electrical characteristics . iii v r os bal lm ls os ibal sense () () == ? r r rirr ds on ta ta l ja tempco () () () ( = ? 25 25 2 1 ? iii r r main nd main main nd ?? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 1 f vv tvv v sw out drop on in drop drop = + () + ? 1 12 () dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 20 ______________________________________________________________________________________ preliminary ton connection frequency setting (khz) k-factor (s) max k-factor error (%) v cc 200 5 10 float 300 3.3 10 ref 550 1.8 12.5 gnd 1000 1.0 12.5 table 3. approximate k-factor errors confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
the worst-case current mismatch occurs immediately after a load transient due to inductor value mismatches resulting in different di/dt for the two phases. the time it takes the current-balance loop to correct the transient imbalance depends on the mismatch between the inductor values and switching frequency. dual 180 out-of-phase operation the two phases in the MAX1987/max1988 operate 180 out-of-phase to minimize input and output filtering requirements, reduce electromagnetic interference (emi), and improve efficiency. this effectively lowers component count reducing cost, board space, and component power requirements making the MAX1987/max1988 ideal for high-power, cost-sensitive applications. typically, switching regulators provide transfer power using only one phase instead of dividing the power among several phases. in these applications, the input capacitors must support high-instantaneous current requirements. the high rms ripple current can lower efficiency due to i 2 r power loss associated with the input capacitor s effective series resistance (esr). therefore, the system typically requires several low- esr input capacitors in parallel to minimize input volt- age ripple, to reduce esr-related power losses, and to meet the necessary rms ripple-current rating. with the MAX1987/max1988, the controller shares the current between two phases that operate 180 out-of- phase, so the high-side mosfets never turn on simulta- neously during normal operation. the instantaneous input current of either phase is effectively halved, result- ing in reduced input-voltage ripple, esr power loss, and rms ripple current (see the input capacitor selection section). therefore, the same performance can be achieved with fewer or less expensive input capacitors. transient overlap operation when a transient occurs, the response time of the con- troller depends on how quickly it can slew the inductor current. multiphase controllers that remain 180 out-of- phase when a transient occurs actually respond slower than an equivalent single-phase controller. in order to provide fast transient response, the MAX1987/ max1988 support a phase overlap mode that allows the individual phases to operate simultaneously when heavy load transients are detected, effectively reducing the response time. after either high-side mosfet turns off, if the output voltage does not exceed the regulation voltage when the minimum off-time expires, the con- troller simultaneously turns on both high-side mosfets during the next on-time cycle. this maximizes the total inductor current slew rate. the phases remain over- lapped until the output voltage exceeds the regulation voltage after the minimum off-time expires. after the phase overlap mode ends, the controller automat- ically begins with the opposite phase. for example, if the secondary phase provided the last on-time pulse before overlap operation began, the controller starts switching with the main phase when overlap operation ends. integrator amplifiers/output voltage offsets two transconductance amplifiers provide a fine adjust- ment to the output regulation point (figure 2). one amplifier forces the dc average of the feedback volt- age to equal the vid dac setting. the second amplifier is used to create small positive or negative offsets from the vid dac setting, using the pos and neg pins. the feedback amplifier integrates the feedback volt- age, allowing accurate dc output voltage regulation regardless of the output ripple voltage. the feedback amplifier has the ability to shift the output voltage by 8%. the differential input voltage range is at least 80mv total, including dc offset and ac ripple. the integration time constant can be set easily with one capacitor at the ccv pin. use a capacitor value of 47pf to 1000pf (270pf typ). the pos/neg amplifier is used to add small offsets to the vid dac setting in deep-sleep mode ( dpslp = low). the offset amplifier is summed directly with the feedback voltage, making the offset gain independent of the dac code. this amplifier has the ability to offset the output by 200mv. to create an output offset, bias pos and neg to a voltage (typically v out or ref) with- in their 0 to 2v common-mode range, and offset them from one another with a resistive divider (figure 1). if v pos is higher than v neg , then the output is shifted in the positive direction. if v neg is higher than v pos , then the output is shifted in the negative direction. the out- put offset equals the voltage difference from pos to neg. forced-pwm operation (normal mode) during normal mode, when the cpu is actively running (sus = low, dpslp = high, psi = high), the MAX1987/ max1988 operate with the low-noise forced-pwm con- trol scheme. forced-pwm operation disables the zero- crossing comparator, forcing the low-side gate-drive waveform to constantly be the complement of the high- side gate-drive waveform. the benefit of forced-pwm mode is to keep the switching frequency fairly constant. forced-pwm operation comes at a cost: the no-load 5v bias supply current remains between 10ma to 100ma, depending on the external mosfets and switching MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies ______________________________________________________________________________________ 21 preliminary confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 22 ______________________________________________________________________________________ MAX1987 max1988 csn csp cmp cmn vcc ref gnd ccv pos neg fb oain+ oain- time 6 bits blank skip ilim 19r r ref (2.0v) shdn ref g m g m dpslp r-2r dac internal multiplexers, mode control, and slew-rate control b0 to b2 s0 to s2 d0?5 sus syspok psi dd0 0.9 x ref 1.1 x ref syspok clken imvpok startup delay q q t cmp cmn skip fault 1.5mv s r q r s q main main on-time one-shot trig q on-time one-shot trig q bstm ton v+ cci dhm lxm v dd dlm pgnd main phase drivers trig q one-shot minimum off-time secondary phase drivers fb g m g m cmp csp cmn csn bsts dhs lxs dls figure 2. MAX1987/max1988 functional diagram confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
frequency. to maintain high efficiency under light-load conditions, the MAX1987/max1988 automatically switch to the low-power pulse-skipping control scheme after entering suspend or deep-sleep mode. during output voltage and mode transitions ( psi = high), the MAX1987/max1988 use forced-pwm opera- tion to ensure fast, accurate transitions. since forced- pwm operation disables the zero-crossing comparator, the inductor current reverses under light loads, quickly discharging the output capacitors. the controller main- tains forced-pwm operation for 32 clock cycles (set by r time ) after the controller sets the last dac code value to guarantee the output voltage settles properly before entering pulse-skipping operation. low-power pulse skipping during deep-sleep mode ( dpslp = low), low-power suspend (sus = high), or pulse-skipping override mode ( psi = low), the MAX1987/max1988 use an automatic pulse-skipping control scheme, alternately switching both phases in order to maintain the current balance. for deep-sleep mode, when the cpu pulls dpslp low, the MAX1987/max1988 shift the output voltage to incorporate the offset voltage set by the pos and neg inputs (figure 3). 32 r time clock cycles after dpslp goes low, the controller pulls the driver-disable output ( ddo ) low. an additional 30 r time clock cycles later, the MAX1987/max1988 enter low-power operation, allowing automatic pulse skipping under light loads. when the cpu drives dpslp high, the MAX1987/ max1988 immediately enter forced-pwm operation, force ddo high, and eliminate the output offset, slew- ing the output to the operating voltage set by the d0 d5 inputs. when either dpslp transition occurs, the MAX1987/max1988 force imvpok high and clken low for 32 r time clock cycles. when entering suspend mode (sus driven high), the MAX1987/max1988 slew the output down to the sus- pend output voltage set by s0 to s2 inputs (figure 4). 32 r time clock cycles after the slew-rate controller reaches the last dac code (see the output voltage transition timing section), the ddo is asserted low. after an additional 30 r time clock cycles, the MAX1987/max1988 enter low-power operation, allow- ing pulse skipping under light loads. when the cpu pulls sus low, the MAX1987/max1988 immediately enter forced-pwm operation, force ddo high, and slew the output up to the operating voltage set by the d0 d5 inputs. when either sus transition occurs, the MAX1987/max1988 blank imvpok and clken , pre- venting imvpok from going low and clken from going high. the blanking remains active until the slew rate controller has reached the last dac code and 32 addi- tional r time clock pulses have passed. when psi is pulled low, the MAX1987/max1988 over- ride forced-pwm operation and use the automatic pulse-skipping control scheme regardless of the state of the sus and dpslp control inputs. once psi is pulled low, the controller asserts the driver-disable out- put ( ddo = low), forces imvpok high, and forces clken low. when psi is used during mode transitions, the constant imvpok and clken blanking allows indefinite settling times. in applications with more than two phases, the driver- disable signal is used to force one or more slave regula- tors into a high-impedance state. when the master s ddo output is driven low, the slave controller with driver disable (max1980) forces its dl (slave) and dh (slave) gate drivers low, effectively disabling the slave con- troller. disabling the slave controller allows the MAX1987/max1988 to enter low-power pulse skipping operation under low-power conditions, improving light- load efficiency. when ddo is driven high, the slave con- troller (max1980) enables the drivers, allowing normal forced-pwm operation. for detailed operation with slave controllers, refer to the max1980 data sheet. automatic pulse-skipping switchover in skip mode ( psi = low, sus = high, or dpslp = low), an inherent automatic switchover to pfm takes place at light loads (figure 5). this switchover is affected by a comparator that truncates the low-side switch on time at the inductor current s zero crossing. the zero-crossing comparator senses the inductor current across the cur- rent-sense resistors. once v c_p - v c_n drops below 1.5mv (typ), the comparator forces dl_ low (figure 2). this mechanism causes the threshold between pulse- skipping pfm and nonskipping pwm operation to coin- cide with the boundary between continuous and discontinuous inductor-current operation. the pfm/pwm crossover occurs when the load current of each phase is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (figure 6). for a battery input range of 7v to 20v, this threshold is relatively con- stant, with only a minor dependence on the input voltage due to the typically low duty cycles. the total load current at the pfm/pwm crossover threshold (i load(skip) ) is approximately: where k is the on-time scale factor (table 3). i vk l vv v load skip out in out in () = ? ? ? ? ? ? ? ? ? ? ? ? ? MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies ______________________________________________________________________________________ 23 preliminary confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 24 ______________________________________________________________________________________ v out time clock imvpok lx_ pulse skipping automatic pulse- skipping switchover output transition and settling output transition and settling dpslp ddo clken t dd0 = 32 clks t skip = 30 clks t blank = 32 clks imvpok and clken blanking imvpok and clken blanking v pos - v neg offset figure 3. MAX1987/max1988 deep sleep transition sus v out time clock imvpok lx_ pulse skipping automatic pulse- skipping switchover output settling output transition output settling output transition output set by s0 to s2 output set by d0 d5 clken ddo 16mv per r time cycle t blank = 32 clks t skip = 30 clks t slew t slew t dd0 = 30 clks imvpok and clken blanking imvpok and clken blanking figure 4. MAX1987/max1988 suspend transition confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
for example, in the standard application circuit this becomes: the switching waveforms can appear noisy and asyn- chronous when light loading activates pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs between pfm noise and light-load efficiency are made by varying the inductor value. generally, low inductor values pro- duce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output volt- age ripple. penalties for using higher inductor values include larger physical size and degraded load-tran- sient response, especially at low-input voltage levels. current-limit circuit the current-limit circuit employs a unique valley cur- rent-sensing algorithm that uses current-sense resistors from cmp to cmn and from csp to csn as the current- sensing elements (figure 1). if the current-sense signal of the selected phase is above the current-limit thresh- old, the pwm controller does not initiate a new cycle (figure 2) until the inductor current of the selected phase drops below the valley current-limit threshold. when either phase trips the current limit, both phases are effectively current limited since the interleaved con- troller does not initiate a cycle with either phase. since only the valley current is actively limited, the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. therefore, the exact current-limit characteristic and maximum load capability are a function of the cur- rent-sense resistance, inductor value, and battery volt- age. when combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance. there is also a negative current limit that prevents excessive reverse inductor currents when v out is sink- ing current. the negative current-limit threshold is set to approximately 120% of the positive current limit, and therefore tracks the positive current limit when ilim is adjusted. when a phase drops below the negative cur- rent limit, the controller immediately activates an on- time pulse dl_ turns off, and dh_ turns on allowing the inductor current to remain above the negative cur- rent threshold. the current-limit threshold is adjusted with an external resistive voltage-divider at ilim. the current-limit thresh- old voltage adjustment range is from 10mv to 75mv. in the adjustable mode, the current-limit threshold voltage is precisely 1/20th the voltage seen at ilim. the thresh- old defaults to 30mv when ilim is connected to v cc . the logic threshold for switchover to the 30mv default value is approximately v cc - 1v. carefully observe the pc board layout guidelines to ensure that noise and dc errors do not corrupt the cur- rent-sense signals seen by the current-sense inputs (cmp, cmn, csp, csn). mosfet gate drivers (dh, dl) the dh_ and dl_ drivers are optimized for driving moderately sized, high-side and larger, low-side power mosfets. this is consistent with the low duty factor seen in the notebook cpu environment, where a large v in - v out differential exists. an adaptive dead-time circuit monitors the dl_ output and prevents the high- side fet from turning on until dl_ is fully off. there must 13 33 06 12 1 3 12 64 .. . . . vs h vv v a ? ? ? ? ? ? ? ? ? ? ? ? = ? MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies ______________________________________________________________________________________ 25 preliminary inductor current i load = i peak /2 on-time 0 time i peak l v batt - v out ? i ? t = figure 5. pulse-skipping/discontinuous crossover point inductor current i limit(valley) = i load(max) 2 - lir 2 () time 0 i peak i load i limit figure 6. valley current-limit threshold point confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
MAX1987/max1988 be a low-resistance, low-inductance path from the dl_ driver to the mosfet gate in order for the adaptive dead-time circuit to work properly. otherwise, the sense circuitry in the MAX1987/max1988 interprets the mosfet gate as off while there is actually charge still left on the gate. use very short, wide traces (50mils to 100mils wide if the mosfet is 1in from the device). the dead time at the other edge (dh_ turning off) is deter- mined by a fixed 35ns internal delay. the internal pulldown transistor that drives dl_ low is robust, with a 0.4 ? (typ) on-resistance. this helps pre- vent dl from being pulled up due to capacitive cou- pling from the drain to the gate of the low-side mosfets when lx_ switches from ground to v in . applications with high input voltages and long, induc- tive dl_ traces can require additional gate-to-source capacitance to ensure fast rising lx_ edges do not pull up the low-side mosfets gate voltage, causing shoot- through currents. the capacitive coupling between lx_ and dl_ created by the mosfets gate-to-drain capacitance (c rss ), gate-to-source capacitance (c iss - c rss ), and additional board parasitics should not exceed the minimum threshold voltage: lot-to-lot variation of the threshold voltage can cause problems in marginal designs. typically, adding a 4700pf between dl_ and power ground (c nl in figure 7), close to the low-side mosfets, greatly reduces coupling. do not exceed 22nf of total gate capacitance to prevent excessive turn-off delays. alternatively, shoot-through currents can be caused by a combination of fast high-side mosfets and slow low- side mosfets. if the turn-off delay time of the low-side mosfet is too long, the high-side mosfets can turn on before the low-side mosfets have actually turned off. adding a resistor less than 5 ? in series with bst_ slows down the high-side mosfet turn-on time, elimi- nating the shoot-through currents without degrading the turn-off time (r bst in figure 7). slowing down the high-side mosfet also reduces the lx node rise time, thereby reducing emi and high-frequency coupling responsible for switching noise. voltage-positioning amplifier the MAX1987/max1988 include an independent op amp for adding gain to the voltage positioning sense path. the voltage-positioning gain allows the use of low-value, current-sense resistors in order to minimize power dissipation. this 3mhz gain-bandwidth amplifier was designed with low offset voltage (70v typ) to meet the imvp-iv output accuracy requirements. the inverting (oain-) and noninverting (oain+) inputs are used to differentially sense the voltage across the voltage-positioning sense resistor. the op amp s output is internally connected to the regulator s feedback input (fb). the op amp should be configured as a noninvert- ing, differential amplifier as shown in figures 1 and 10. the voltage-positioning slope is set by properly selecting the feedback resistor connected from fb to oain- (see the setting voltage positioning section). for applications using a slave controller, additional differential input resis- tors (summing configuration) should be connected to the slave s voltage-positioning sense resistor (figures 1 and 10). summing together both the master and slave cur- rent-sense signals ensures that the voltage-positioning slope remains constant when the slave controller is dis- abled. in applications that do not require voltage positioning gain, the amplifier can be disabled by connecting the oain- pin directly to v cc . the disabled amplifier s out- put becomes high impedance, guaranteeing that the unused amplifier does not corrupt the fb input signal. the logic threshold to disable the op amp is approxi- mately v cc - 1v. power-up sequence the MAX1987/max1988 are enabled when shdn is dri- ven high (figure 8). first, the reference powers up. once vv c c gs th in rss iss () < ? ? ? ? ? ? dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 26 ______________________________________________________________________________________ MAX1987 max1988 v dd bst dh lx (r bst )* (c nl )* d bst c bst c byp input (v in ) n h l v dd dl pgnd n l (r bst )* optional the resistor lowers emi by decreasing the switching node rise time. (cnl)* optional the capacitor reduces lx to dl capacitive coupling that can cause shoot through currents. figure 7. optional gate driver circuitry confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
the reference exceeds its undervoltage lockout thresh- old, the pwm regulator becomes active. the slew-rate controller ramps up the output voltage in 16mv incre- ments to the selected boot code value (b0 to b2, table 7). the ramp rate is set with the r time resistor (see the output voltage transition timing section). syspok serves as the combined power-good input for v ccp and v ccmch . once these supplies are within 10% of their output voltage, their power-good outputs become high impedance, allowing syspok to be pulled high. approximately 50s after the MAX1987/ max1988 detect both a logic high voltage on syspok and the slew-rate controller reaches the dac code set by b0 to b2, the controller pulls clken low and slews the output to the proper operating voltage (table 4). when clken goes low, the MAX1987/max1988 keep imvpok low for an additional 3ms (min), guaranteeing that the cpu has time to start properly. if the MAX1987/ max1988 do not detect a fault, then imvpok is pulled high once the 3ms timer expires. power-on reset power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch, activating boot mode, and preparing the pwm for operation. v cc undervoltage lockout (uvlo) circuitry inhibits switch- ing, and forces the dl gate driver high (to enforce out- put overvoltage protection). when v cc rises above 4.25v, the dac inputs are sampled and the output volt- age begins to slew to the boot voltage (table 7). for automatic startup, the battery voltage should be present before v cc . if the MAX1987/max1988 attempt to bring the output into regulation without the battery voltage present, the fault latch trips. the shdn pin can be toggled to reset the fault latch. input undervoltage lockout during startup, the v cc uvlo circuitry forces the dl gate driver high and the dh gate driver low, inhibiting switching until an adequate supply voltage is reached. once v cc rises above 4.25v, valid transitions detected at the trigger input initiate a corresponding on-time pulse (see the on-time one-shot section). if the v cc voltage drops below 4.25v, it is assumed that there is not enough supply voltage to make valid decisions. to protect the output from overvoltage faults, dl is forced high in this mode, to force the output to ground. this results in large negative inductor current and possibly small negative output voltages. if v cc is likely to drop in this fashion, the output can be clamped with a schottky diode to pgnd to reduce the negative excursion. shutdown when shdn or syspok goes low, the MAX1987/ max1988 enter low-power shutdown mode. imvpok is pulled low and clken is driven high immediately. the MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies ______________________________________________________________________________________ 27 preliminary vid (d0 d5) v ccp v core v ccp power-ok v cc_mch syspok imvpok t imvpok -12% -12% v cc_mch power-ok soft-start shdn clken t clken figure 8. power-up sequence timing diagram confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
MAX1987/max1988 output voltage ramps down to 0v in 16mv steps at the clock rate set by r time . when the dac reaches the 0v setting, dl goes high, dh goes low, the reference is turned off, the boot mode latch is cleared, and the sup- ply current drops to about 1a. when a fault condition (output undervoltage lockout, thermal shutdown, or a falling edge on syspok) activates the shutdown sequence, the controller sets the fault latch to prevent the controller from restarting. to clear the fault latch and reactivate the MAX1987/max1988, toggle shdn or cycle v cc power below 1v. when shdn goes high, the reference powers up, and after the reference uvlo is passed, the dac target is evaluated and switching begins. the slew-rate con- troller ramps up from 0v in 16mv steps to the currently selected boot-code value (see the power-up sequence section). there is no traditional soft-start (variable cur- rent limit) circuitry, so full output current is available immediately. internal multiplexers the MAX1987/max1988 have two unique internal dac input multiplexers (muxes) that can select one of three different dac code settings for different processor states, depending on the power-up sequence and sus state. on startup, the controller selects the dac code from the b0 to b2 (sus = low) or s0 to s2 (sus = high) input decoder (figure 9). once syspok goes high and the MAX1987/max1988 properly regulate to the boot voltage, a second multiplexer selects the dac code from either d0 d5 (sus = low) or s0 to s2 (sus = high). dac inputs (d0?5) during normal operation (sus = low), the digital-to-ana- log converter (dac) programs the output voltage using the d0 d5 inputs. d0 d5 are low-voltage (1v) logic inputs, designed to interface directly with the imvp-iv cpu. do not leave d0 d5 unconnected. d0 d5 can be changed while the MAX1987/max1988 are active, initi- ating a transition to a new output voltage level. change d0 d5 together, avoiding greater than 1s skew between bits. otherwise, incorrect dac readings can cause a partial transition to the wrong voltage level fol- lowed by the intended transition to the correct voltage level, lengthening the overall transition time. the avail- able dac codes and resulting output voltages (table 5) are compatible with imvp-iv specification. four-level logic inputs ton, b0 to b2, and s0 to s2 are four-level logic inputs. these inputs help expand the functionality of the con- troller without adding an excessive number of pins. the four-level inputs are intended to be static inputs. when left open, an internal resistive voltage-divider sets the input voltage to approximately 3.5v. therefore, connect the four-level logic inputs directly to vcc, ref, or gnd when selecting one of the other logic levels. see the electrical characteristics for exact logic-level voltages. dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 28 ______________________________________________________________________________________ preliminary d0 d1 d2 d3 d4 d5 s0 s1 s2 s0 to s2 decoder in out b0 b1 b2 b0 to b2 decoder in out sus syspok suspend mux boot mux out 1 0 1 0 sel sel trig q t syspok one-shot out dac figure 9. internal multiplexers block diagram confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies ______________________________________________________________________________________ 29 table 4. operating mode truth table shdn syspok sus dpslp ddo psi output voltage operating mode 0xxx0xgnd low-power shutdown mode. dl is forced high, dh is forced low, and the pwm controller is disabled. the supply current drops to 1a. 100x1x b0 to b2 (no offset) power-up mode. when enabled, the MAX1987/ max1988 softly ramp up the output voltage to the selected boot voltage (b0 to b2, table 7). the controller remains at the boot voltage until syspok is driven high (see the power-up sequence section). 110111 d0 d5 (no offset) normal operation. the no-load output voltage is determined by the selected vid dac code (d0 d5, table 5). 110100 d0 d5 (no offset) pulse-skipping override. when psi is pulled low, the MAX1987/max1988 immediately enter pulse-skipping operation allowing automatic pwm/pfm switchover under light loads. the imvpok output is forced high, and the clken output is forced low as long as psi is pulled low. 11000x d0 d5 (plus offset) deep-sleep mode. the no-load output voltage is determined by the selected vid dac code (d0 d5, table 5) plus the offset voltage set by pos and neg. operation with automatic pwm/pfm switchover for pulse-skipping under light loads. 1x1x0x s0 to s2 (no offset) suspend mode. the no-load output voltage is determined by the selected suspend code (s0 to s2, table 6), overriding all other active modes of operation. operation with automatic pwm/pfm switchover for pulse-skipping under light loads. 10xx0xgnd fault mode. the fault latch has been set by either uvp, ovp (MAX1987 only), thermal shutdown, or a falling edge on syspok. the controller remains in fault mode until v cc power is cycled or shdn toggled. confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 30 ______________________________________________________________________________________ preliminary table 5. output voltage vid dac codes (sus = low) d5 d4 d3 d2 d1 d0 output voltage (v) 000000 1.708 000001 1.692 000010 1.676 000011 1.660 000100 1.644 000101 1.628 000110 1.612 000111 1.596 001000 1.580 001001 1.564 001010 1.548 001011 1.532 001100 1.516 001101 1.500 001110 1.484 001111 1.468 010000 1.452 010001 1.436 010010 1.420 010011 1.404 010100 1.388 010101 1.372 010110 1.356 010111 1.340 011000 1.324 011001 1.308 011010 1.292 011011 1.276 011100 1.260 011101 1.244 011110 1.228 011111 1.212 d5 d4 d3 d2 d1 d0 output voltage (v) 1 0 0 0 0 0 1.196 1 0 0 0 0 1 1.180 1 0 0 0 1 0 1.164 1 0 0 0 1 1 1.148 1 0 0 1 0 0 1.132 1 0 0 1 0 1 1.116 1 0 0 1 1 0 1.100 1 0 0 1 1 1 1.084 1 0 1 0 0 0 1.068 1 0 1 0 0 1 1.052 1 0 1 0 1 0 1.036 1 0 1 0 1 1 1.020 1 0 1 1 0 0 1.004 1 0 1 1 0 1 0.988 1 0 1 1 1 0 0.972 1 0 1 1 1 1 0.956 1 1 0 0 0 0 0.940 1 1 0 0 0 1 0.924 1 1 0 0 1 0 0.908 1 1 0 0 1 1 0.892 1 1 0 1 0 0 0.876 1 1 0 1 0 1 0.860 1 1 0 1 1 0 0.844 1 1 0 1 1 1 0.828 1 1 1 0 0 0 0.812 1 1 1 0 0 1 0.796 1 1 1 0 1 0 0.780 1 1 1 0 1 1 0.764 1 1 1 1 0 0 0.748 1 1 1 1 0 1 0.732 1 1 1 1 1 0 0.716 1 1 1 1 1 1 0.700 confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies ______________________________________________________________________________________ 31 preliminary table 6. suspend mode dac codes (sus = high) s2 s1 s0 output voltage (v) gnd gnd gnd 1.452 gnd gnd ref 1.436 gnd gnd open 1.420 gnd gnd v cc 1.404 gnd ref gnd 1388 gnd ref ref 1.372 gnd ref open 1.356 gnd ref v cc 1.340 gnd open gnd 1.324 gnd open ref 1.308 gnd open open 1.292 gnd open v cc 1.276 gnd v cc gnd 1.260 gnd v cc ref 1.244 gnd v cc open 1.228 gnd v cc v cc 1.212 ref gnd gnd 1.196 ref gnd ref 1.180 ref gnd open 1.164 ref gnd v cc 1.148 ref ref gnd 1.132 ref ref ref 1.116 ref ref open 1.100 ref ref v cc 1.084 ref open gnd 1.068 ref open ref 1.052 ref open open 1.036 ref open v cc 1.020 ref v cc gnd 1.004 ref v cc ref 0.988 ref v cc open 0.972 ref v cc v cc 0.956 s2 s1 s0 output voltage (v) open gnd gnd 0.940 open gnd ref 0.924 open gnd open 0.908 open gnd v cc 0.892 open ref gnd 0.876 open ref ref 0.860 open ref open 0.844 open ref v cc 0.828 open open gnd 0.812 open open ref 0.796 open open open 0.780 open open v cc 0.764 open v cc gnd 0.748 open v cc ref 0.732 open v cc open 0.716 open v cc v cc 0.700 v cc gnd gnd 0.684 v cc gnd ref 0.668 v cc gnd open 0.652 v cc gnd v cc 0.636 v cc ref gnd 0.620 v cc ref ref 0.604 v cc ref open 0.588 v cc ref v cc 0.572 v cc open gnd 0.556 v cc open ref 0.540 v cc open open 0.524 v cc open v cc 0.508 v cc v cc gnd 0.492 v cc v cc ref 0.476 v cc v cc open 0.460 v cc v cc v cc 0.444 confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 32 ______________________________________________________________________________________ preliminary table 7. boot mode dac codes (power-up) b2 b1 b0 output voltage (v) gnd gnd gnd 1.708 gnd gnd ref 1.692 gnd gnd open 1.676 gnd gnd v cc 1.660 gnd ref gnd 1.644 gnd ref ref 1.628 gnd ref open 1.612 gnd ref v cc 1.596 gnd open gnd 1.580 gnd open ref 1.564 gnd open open 1.548 gnd open v cc 1.532 gnd v cc gnd 1.516 gnd v cc ref 1.500 gnd v cc open 1.484 gnd v cc v cc 1.468 ref gnd gnd 1.452 ref gnd ref 1.436 ref gnd open 1.420 ref gnd v cc 1.404 ref ref gnd 1.388 ref ref ref 1.372 ref ref open 1.356 ref ref v cc 1.340 ref open gnd 1.324 ref open ref 1.308 ref open open 1.292 ref open v cc 1.276 ref v cc gnd 1.260 ref v cc ref 1.244 ref v cc open 1.228 ref v cc v cc 1.212 b2 b1 b0 output voltage (v) open gnd gnd 1.196 open gnd ref 1.180 open gnd open 1.164 open gnd v cc 1.148 open ref gnd 1.132 open ref ref 1.116 open ref open 1.100 open ref v cc 1.084 open open gnd 1.068 open open ref 1.052 open open open 1.036 open open v cc 1.020 open v cc gnd 1.004 open v cc ref 0.988 open v cc open 0.972 open v cc v cc 0.956 v cc gnd gnd 0.940 v cc gnd ref 0.924 v cc gnd open 0.908 v cc gnd v cc 0.892 v cc ref gnd 0.876 v cc ref ref 0.860 v cc ref open 0.844 v cc ref v cc 0.828 v cc open gnd 0.812 v cc open ref 0.796 v cc open open 0.780 v cc open v cc 0.764 v cc v cc gnd 0.748 v cc v cc ref 0.732 v cc v cc open 0.716 v cc v cc v cc 0.700 confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
suspend mode when the processor enters low-power suspend mode, the processor sets the regulator to a lower output volt- age to reduce power consumption. the MAX1987/ max1988 include independent suspend mode output voltage codes set by the four-level inputs s0 to s2. when the cpu suspends operation, sus is driven high, overriding the 6-bit vid dac code set by either d0 d5 (normal operation) or b0 to b2 (power-up). the master controller slews the output to the selected suspend mode voltage. during the transition, the MAX1987/ max1988 assert forced-pwm operation until 62 r time clock cycles (t ddo + t skip ) after the slew-rate controller reaches the suspend mode voltage. when sus is low during normal operation (syspok = high), the output voltage is dynamically controlled by the 6-bit vid dac inputs (d0 d5). output voltage transition timing the MAX1987/max1988 are designed to perform mode transitions in a controlled manner, automatically mini- mizing input surge currents. this feature allows the cir- cuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output volt- age level with the lowest possible peak currents for a given output capacitance. this makes the ic ideal for imvp-iv cpus. at the beginning of an output voltage transition, the MAX1987/max1988 blank the imvpok and clken out- puts, preventing them from changing states. imvpok and clken remain blanked during the transition and are re-enabled 32 clock cycles after the slew-rate controller has set the final dac code value. the slew-rate clock frequency (set by the resistor r time ) must be set fast enough to ensure that the transition is completed within the maximum allotted time. the slew-rate controller transitions the output voltage in 16mv increments during soft-start, soft shutdown, and suspend mode transitions. the total time for a transition depends on r time , the voltage difference, and the accu- racy of the MAX1987/max1988s slew-rate clock, and is not dependent on the total output capacitance. the greater the output capacitance, the higher the surge cur- rent required for the transition. the MAX1987/max1988 automatically control the current to the minimum level required to complete the transition in the calculated time, as long as the surge current is less than the current limit set by ilim. the transition time is given by: where f slew = 320khz ? 47k ? / r time , v old is the original dac setting, and v new is the new dac setting. the additional 2 clock cycles on the falling edge time are due to internal synchronization delays. see time frequency accuracy in the electrical characteristics for f slew limits. the practical range of r time is 23.5k ? to 235k ? corre- sponding with 1.6s to 15.6s per 16mv step. although the dac takes discrete 16mv steps, the output filter makes the transitions relatively smooth. the average inductor current required to make an output-voltage transition is: i l ? c out ? 16mv ? f slew output overvoltage protection (MAX1987 only) the overvoltage protection (ovp) circuit is designed to protect the cpu against a shorted high-side mosfet by drawing high current and blowing the battery fuse. the output voltage is continuously monitored for over- voltage. if the actual fb voltage exceeds 2v, the ovp circuit immediately forces the dl low-side gate-driver high, pulls the dh high-side gate-driver low, sets the fault latch, and shuts down the pwm controller. this action turns on the synchronous-rectifier mosfet with 100% duty and, in turn, rapidly discharges the output fil- ter capacitor and forces the output to ground. if the con- dition that caused the overvoltage (such as a shorted high-side mosfet) persists, the battery fuse blows. when the fault latch is activated, the controller pulls imvpok low and drives clken high. the controller remains shut down until the fault latch is cleared by tog- gling shdn or cycling the v cc power supply below 1v. overvoltage protection can be disabled through the no fault test mode (see the no fault test mode section). output undervoltage shutdown the output uvp function is similar to foldback-current- limiting, but employs a timer rather than a variable cur- rent limit. if the MAX1987/max1988 output voltage is under 70% of the nominal value, the controller activates the shutdown sequence and sets the fault latch. once the controller ramps down to the 0v dac code setting, it forces the dl low-side gate-driver high, and pulls the t f vv mv for v ri g t f vv mv for v falling slew slew new old out slew slew old new out ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? 1 16 1 16 2 sin MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies ______________________________________________________________________________________ 33 preliminary confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
MAX1987/max1988 dh high-side gate-driver low. toggle shdn or cycle the v cc power supply below 1v to clear the fault latch and reactivate the controller. uvp is ignored during out- put voltage transitions and remains blanked for an additional 32 clock cycles after the controller reaches the final dac code value. uvp can be disabled through the no fault test mode (see the no fault test mode section). thermal fault protection the MAX1987/max1988 feature a thermal fault protec- tion circuit. when the junction temperature rises above +160 c, a thermal sensor activates the fault latch and activates the soft shutdown sequence. once the con- troller ramps down to the 0v dac code setting, it forces the dl low-side gate-driver high, and pulls the dh high-side gate-driver low. toggle shdn or cycle the v cc power supply below 1v to clear the fault latch and reactivate the controller after the junction temperature cools by 15 c. thermal shutdown can be disabled through the no fault test mode (see the no fault test mode section). no fault test mode the latched fault protection features and overlap mode can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. therefore, a no fault test mode is provided to disable the overvoltage protection (MAX1987), undervoltage protection, thermal shutdown, and overlap mode. additionally, the test mode clears the fault latch if it has been set. the no fault test mode is entered by forcing 12v to 15v on shdn . design procedure firmly establish the input-voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing four factors dictate the rest of the design: input-voltage range: the maximum value (v in(max) ) must accommodate the worst-case high ac-adapter voltage. the minimum value (v in(min) ) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. if there is a choice at all, lower input voltages result in better efficiency. maximum load current: there are two values to con- sider. the peak load current (i load(max) ) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selec- tion, inductor saturation rating, and the design of the current-limit circuit. the continuous load current (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other criti- cal heat-contributing components. modern notebook cpus generally exhibit i load = i load(max) ? 80%. for multiphase systems, each phase supports a frac- tion of the load, depending on the current balancing. when properly balanced, the load current is evenly dis- tributed among each phase: switching frequency: this choice determines the basic trade-off between size and efficiency. the opti- mal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are pro- portional to frequency and v in 2 . the optimum frequen- cy is also a moving target, due to rapid improvements in mosfet technology that are making higher frequen- cies more practical. inductor operating point: this choice provides trade- offs between size vs. efficiency and transient response vs. output noise. low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. the minimum practical induc- tor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size- reduction benefit. the optimum operating point is usu- ally found between 20% and 50% ripple current. inductor selection the switching frequency and operating point (% ripple or lir) determine the inductor value as follows: example: i load(max) = 40a, v in = 12v, v out = 1.3v, f sw = 300khz, 30% ripple current or lir = 0.3. find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the l vvv v khz a h = = ? 213 12 13 12 300 40 0 3 064 .( .) . . l vv f i lir v v in out sw load max out in = ? ? ? ? ? ? ? ? ? ? ? ? ? 2 () ii i load main load nd load () () == 2 2 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 34 ______________________________________________________________________________________ preliminary confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
core must be large enough not to saturate at the peak inductor current (i peak ). transient response the inductor ripple current impacts transient-response performance, especially at low v in - v out differentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output fil- ter capacitors by a sudden load step. the amount of output sag is also a function of the maximum duty fac- tor, which can be calculated from the on time and mini- mum off-time: where t off(min) is the minimum off-time (see the electrical characteristics section) and k is from table 3. the amount of overshoot due to stored inductor energy can be calculated as: setting the current limit the minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at i load(max) minus half the ripple current; therefore: where i limit(low) equals the minimum current-limit threshold voltage divided by the current-sense resistor (r sense ). for the 30mv default setting, the minimum current-limit threshold is 27mv. connect ilim to v cc for a default 30mv current-limit threshold. in adjustable mode, the current-limit thresh- old is precisely 1/20th the voltage seen at ilim. for an adjustable threshold, connect a resistive divider from ref to gnd with ilim connected to the center tap. the external 200mv to 1.5v adjustment range corresponds to a 10mv to 75mv current-limit threshold. when adjust- ing the current limit, use 1% tolerance resistors with approximately 10a of divider current to prevent a sig- nificant increase of errors in the current-limit tolerance. output capacitor selection the output filter capacitor must have low enough esr to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. in cpu v core converters and other applications where the output is subject to large load transients, the output capacitor s size typically depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: in non-cpu applications, the output capacitor s size often depends on how much esr is needed to maintain an acceptable level of output ripple voltage. the output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capaci- tor s esr. when operating multiphase systems out-of- phase, the peak inductor currents of each phase are staggered, resulting in lower output ripple voltage by reducing the total inductor ripple current. for 180 out- of-phase operation, the maximum esr to meet ripple requirements is: where f sw is the switching frequency per phase. the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chem- istry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of polymer types). when using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load transients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag and v soar equations in the transient response section). r v vv fl v v esr ripple in out sw out in ? ? ? ? ? ? ? ? ? ? ? ? ? 2 r v i esr step load max ? () i i lir limit low load max () () > ? ? ? ? ? ? ? ? ? ? ? ? ? 2 1 2 v il cv soar load max out out () ? () 2 2 v li vk v t cv vvk v t i c vk v t sag load max out in off min out out in out in off min load max out out in off min = ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? + ? ? ? ? ? ? ? ? () () () () () () () ? ? 2 2 2 2 2 i i lir peak load max = ? ? ? ? ? ? + ? ? ? ? ? ? () 2 1 2 MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies ______________________________________________________________________________________ 35 preliminary confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
MAX1987/max1988 output capacitor stability considerations for quick-pwm controllers, stability is determined by the value of the esr zero relative to the switching fre- quency. the boundary of instability is given by the fol- lowing equation: where c out is the total output capacitance, r esr is the total equivalent-series-resistance, r sense is the current- sense resistance (r cm = r cs ), a vps is the voltage posi- tioning gain, and r pcb is the parasitic board resistance between the output capacitors and sense resistors. for a standard 300khz application, the esr zero fre- quency must be well below 95khz, preferably below 50khz. tantalum, sanyo poscap, and panasonic sp capacitors, in wide-spread use at the time of publica- tion, have typical esr zero frequencies below 50khz. in the standard application circuit, the esr needed to support a 30mv p-p ripple is 30mv/(40a ? 0.3) = 2.5m ? . four 330f/2.5v panasonic sp (type xr) capacitors in parallel provide 2.5m ? (max) esr. their typical com- bined esr results in a zero at 40khz. ceramic capacitors have a high esr zero frequency, but applications with significant voltage positioning can take advantage of their size and low esr. don t put high-value ceramic capacitors directly across the out- put without verifying that the circuit contains enough voltage positioning and series pc board resistance to ensure stability. when only using ceramic output capacitors, output overshoot (v soar ) typically deter- mines the minimum output capacitance requirement. their relatively low capacitance value can cause output overshoot when stepping from full-load to no-load con- ditions, unless a small inductor value is used (high switching frequency) to minimize the energy transferred from inductor to capacitor during load-step recovery. the efficiency penalty for operating at 550khz is about 3% when compared to the 300khz circuit, primarily due to the high-side mosfet switching losses. unstable operation manifests itself in two related but dis- tinctly different ways: double pulsing and feedback-loop instability. double pulsing occurs due to noise on the out- put or because the esr is so low that there is not enough voltage ramp in the output voltage signal. this fools the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. double pulsing is more annoying than harmful, resulting in noth- ing worse than increased output ripple. however, it can indicate the possible presence of loop instability due to insufficient esr. loop instability can result in oscillations at the output after line or load steps. such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for over- shoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under/overshoot. input capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents. the MAX1987/max1988 operate 180 out-of-phase, alternating the turn-on times of each phase. this mini- mizes the input ripple current by dividing the load cur- rent between the two phases. the i rms requirements can be determined by the following equation: the worst-case rms current requirement occurs when operating with a 25% duty cycle (v in = 4v out ). at this point, the above equation simplifies to i rms = 0.25 ? i load . when compared to a single-phase regulator, the multiphase converter reduces the rms input current by at least 30%. for most applications, nontantalum chemistries (ceram- ic, aluminum, or os-con) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. if the MAX1987/max1988 are operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. in either con- figuration, choose an input capacitor that exhibits less than +10 c temperature rise at the rms input current for optimal circuit longevity. power mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (>20v) ac adapters. low-current applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at both v in(min) and v in(max) . calculate both of these sums. i i v vvv rms load in out in out = ? ? ? ? ? ? ? 2 22 () f f where f rc and r r a r r esr sw esr eff out eff esr vps sense pcb = =+ + 1 2 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 36 ______________________________________________________________________________________ preliminary confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
ideally, the losses at v in(min) should be roughly equal to losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher than the losses at v in(max) , consider increasing the size of n h . conversely, if the losses at v in(max) are significantly higher than the losses at v in(min) , consider reducing the size of n h . if v in does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. choose a low-side mosfet that has the lowest possible on-resistance (r ds(on) ), comes in a moderate-sized package (i.e., one or two 8-pin sos, dpak, or d 2 pak), and is reasonably priced. make sure that the dl gate dri- ver can supply sufficient current to support the gate charge and the current injected into the parasitic gate-to- drain capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction problems can occur. mosfet power dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet (n h ), the worst- case power dissipation due to resistance occurs at the minimum input voltage: generally, a small high-side mosfet is desired to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power dis- sipation often limits how small the mosfet can be. again, the optimum occurs when the switching losses equal the conduction (r ds(on) ) losses. high-side switching losses do not usually become an issue until the input is greater than approximately 15v. calculating the power dissipation in the high-side mosfet (n h ), due to switching losses, is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pc board layout characteristics. the following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a ther- mocouple mounted on n h : where c rss is the reverse transfer capacitance of n h and i gate is the peak gate-drive source/sink current (1a typ). switching losses in the high-side mosfet can become an insidious heat problem when maximum ac adapter voltages are applied, due to the squared term in the c ? v in 2 ? f sw switching-loss equation. if the high-side mosfet chosen for adequate r ds(on) at low-battery voltages becomes extraordinarily hot when biased from v in(max) , consider choosing another mosfet with lower parasitic capacitance. for the low-side mosfet (n l ), the worst-case power dissipation always occurs at maximum input voltage: the worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) but are not quite high enough to exc eed the current limit and cause the fault latch to trip. to protect against this possibility, you can over design the circuit to tolerate: where i valley(max) is the maximum single-phase val- ley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. the mosfets must have a good size heatsink to handle the overload power dissipation. choose a schottky diode (d1) with a forward voltage low enough to prevent the low-side mosfet body diode from turning on during the dead time. as a gen- eral rule, select a diode with a dc current rating equal to 1/6th of the total load current. this diode is optional and can be removed if efficiency is not critical. boost capacitors the boost capacitors (c bst ) must be selected large enough to handle the gate charging requirements of the high-side mosfets. typically, 0.1f ceramic capacitors work well for low-power applications driving medium-sized mosfets. however, high-current appli- cations driving large, high-side mosfets require boost capacitors larger than 0.1f. for these applications, select the boost capacitors to avoid discharging the capacitor more than 200mv while charging the high- side mosfets gates: where n is the number of high-side mosfets used for one regulator, and q gate is the gate charge specified c nq mv bst gate = 200 ii i lir load valley max load max =+ ? ? ? ? ? ? 2 2 () () pd n sistive v v i r h out in max load ds on (re ) () () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 2 2 pd n switching vcfi i h in max rss sw load gate () () () = 2 2 pd n sistive v v i r h out in load ds on (re ) () = ? ? ? ? ? ? ? ? ? ? ? ? 2 2 MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies ______________________________________________________________________________________ 37 preliminary confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
MAX1987/max1988 in the mosfet s data sheet. for example, assume (2) fds6694 n-channel mosfets are used on the high side. according to the manufacturer s data sheet, a sin- gle fds6694 has a typical gate charge of 13nc (v gs = 5v). using the above equation, the required boost capacitance would be: selecting the closest standard value, this example requires a 0.1f ceramic capacitor. current balance compensation (cci) the current-balance compensation capacitor (c cci ) integrates the difference between the main and sec- ondary current-sense voltages. this capacitor allows the user to optimize the dynamics of the current-bal- ance loop. large capacitor values increase the integra- tion time constant, resulting in larger current differences between the phases during transients. small capacitor values allow the current loop to respond cycle-by-cycle, but can result in small dc current variations between the phases. for most applications, a 470pf capacitor from cci to fb works well. in pulse-skipping operation, the integration time becomes much smaller than the off-time. this allows the offset cur- rent to charge up the cci compensation capacitor, extending the secondary on-time so that a current imbal- ance occurs. add a 470k ? to 1m ? resistor between cci and fb (r cci ) to cancel the offset current. setting voltage positioning voltage positioning dynamically lowers the output voltage in response to the load current, reducing the processor s power dissipation. when the output is loaded, an internal op amp (figures 2 and 10) increases the signal fed back to the MAX1987/max1988s feedback input. the adjustable amplification allows the use of standard, low- value, current-sense resistors, significantly reducing the power dissipated in the current-sense resistors when compared to connecting the feedback voltage directly to the current-sense resistor. the load transient response of this control loop is extremely fast yet well controlled, so the amount of voltage change can be accurately con- fined within the limits stipulated in the microprocessor power-supply guidelines. to understand the benefits of dynamically adjusting the output voltage, see the voltage positioning and effective efficiency section. the voltage-positioned circuit determines the load current from the voltage across the current-sense resistors (r sense = r cm = r cs ) connected between the inductors and output capacitors, as shown in figure 10. the volt- age drop can be determined by the following equation: the current-sense summation maintains the proper 180 out-of-phase operation. select the positive input summing resistors using the following equation: r a = r b // (2r f ) minimum input voltage requirements and dropout performance the output voltage adjustable range for continuous- conduction operation is restricted by the nonadjustable minimum off-time one-shot and the number of phases. for best dropout performance, use the slower (200khz) on-time settings. when working with low input voltages, the duty-factor limit must be calculated using worst- case values for on- and off-times. manufacturing toler- ances and internal propagation delays introduce an error to the ton k-factor. this error is greater at higher frequencies (table 3). also, keep in mind that transient response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the v sag equation in the design procedure section). the absolute point of dropout is when the inductor cur- rent ramps down during the minimum off-time ( ? i down ) as much as it ramps up during the on-time ( ? i up ). the ratio h = ? i up / ? i down is an indicator of the ability to slew the inductor current higher in response to increased load, and must always be greater than 1. as h approach- es 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle and v sag greatly increases unless additional out- put capacitance is used. a reasonable minimum value for h is 1.5, but adjusting this up or down allows tradeoffs between v sag , output capacitance, and minimum operating voltage. for a given value of h, the minimum operating voltage can be calculated as: v r r i r v r r ir vair vps f b load sense vps f b load sense vps vps load sense =+ ? ? ? ? ? ? ? ? ? ? ? ? =+ ? ? ? ? ? ? = 1 2 2 1 2 c nc mv f bst = = 213 200 013 . dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 38 ______________________________________________________________________________________ preliminary confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
where is the number of phases, v vps is the voltage- positioning droop, v drop1 and v drop2 are the para- sitic voltage drops in the discharge and charge paths (see the on-time one-shot section), t off(min) is from the electrical characteristics , and k is taken from table 3. the absolute minimum input voltage is calculated with h = 1. if the calculated v in(min) is greater than the required minimum input voltage, then reduce the operating fre- quency or add output capacitance to obtain an accept- able v sag . if operation near dropout is anticipated, calculate v sag to be sure of adequate transient response. dropout design example: v fb = 1.4v k min = 3.0s for f sw = 300khz t off(min) = 400ns v vps = 3mv/a ? 30a = 90mv v drop1 = v drop2 = 150mv (30a load) h = 1.5 and = 2 calculating again with h = 1 gives the absolute limit of dropout: therefore, v in must be greater than 4.1v, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 5v. v vmv mv ss mv mv mv v in min () . (. . / . ) . = + ? ? ? ? ? ? ? + += ? ? ? 2 1 4 90 150 1 2 04 10 30 150 150 90 4 07 v vmv mv ss mv mv mv v in min () . (. . / . ) . = + ? ? ? ? ? ? ? + += ? ? ? 2 1 4 90 150 1 2 04 15 30 150 150 90 4 96 v vv v ht k vvv in min fb vps drop off min drop drop vps () () = + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + ? ? ? 1 21 1 MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies ______________________________________________________________________________________ 39 r cm l m main phase secondary phase pc board trace resistance error comparator r f l s = l m r cs = r cm MAX1987 max1988 r a r b r a r b oain+ oain- fb figure 10. voltage positioning gain confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
MAX1987/max1988 applications information voltage positioning and effective efficiency powering new mobile processors requires careful attention to detail to reduce cost, size, and power dissi- pation. as cpus became more power hungry, it was recognized that even the fastest dc-dc converters were inadequate to handle the transient power require- ments. after a load transient, the output instantly changes by esr cout ? ? i load . conventional dc-dc converters respond by regulating the output voltage back to its nominal state after the load transient occurs (figure 11). however, the cpu only requires that the output voltage remain above a specified minimum value. dynamically positioning the output voltage to this lower limit allows the use of fewer output capacitors and reduces power consumption under load. for a conventional (nonvoltage-positioned) circuit, the total voltage change is: v p-p1 = (esr cout ? ? i load ) + v sag + v soar where v sag and v soar are defined in figure 12. setting the converter to regulate at a lower voltage when under load allows a larger voltage step when the output current suddenly decreases (figure 11). so the total voltage change for a voltage-positioned circuit is: v p-p2 = (esr cout ? ? i load ) + v sag + v soar where v sag and v soar are defined in the design procedure section. since the amplitudes are the same for both circuits (v p-p1 = v p-p2 ), the voltage-positioned circuit tolerates twice the esr. since the esr specifica- tion is achieved by paralleling several capacitors, fewer units are needed for the voltage-positioned circuit. an additional benefit of voltage positioning is reduced power consumption at high load currents. since the output voltage is lower under load, the cpu draws less current. the result is lower power dissipation in the cpu, although some extra power is dissipated in r sense . for a nominal 1.4v, 30a output (r load = 46.7m ? ), reducing the output voltage 7.1% gives an output voltage of 1.3v and an output current of 27.8a. given these values, cpu power consumption is reduced from 42w to 36.1w. the additional power con- sumption of r sense is: 1.5m ? x (27.8a) 2 = 1.16w which results in an overall power savings of: 42w - (36.1w + 1.16w) = 4.7w in effect, 5.9w of cpu dissipation is saved and the power supply dissipates much of the savings, but both the net savings and the transfer of dissipation away from the hot cpu are beneficial. effective efficiency is defined as the efficiency required of a nonvoltage-posi- tioned circuit to equal the total dissipation of a voltage- positioned circuit for a given cpu operating condition. calculate effective efficiency as follows: 1) start with the efficiency data for the positioned cir- cuit (v in , i in , v out , i out ). 2) model the load resistance for each data point: r load = v out / i out 3) calculate the output current that would exist for each r load data point in a nonpositioned application: i np = v np / r load where v np = 1.6v (in this example). 4) calculate effective efficiency as: effective efficiency = (v np ? i np ) / (v in ? i in ) = calculated nonpositioned power output divided by the measured voltage-positioned power input. 5) plot the efficiency data point at the nonpositioned current, i np . pc board layout guidelines careful pc board layout is critical to achieve low switch- ing losses and clean, stable operation. the switching power stage requires particular attention (figure 13). if possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. follow these guidelines for good pc board layout: 1) keep the high-current paths short, especially at the ground terminals. this is essential for stable, jitter- free operation. dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 40 ______________________________________________________________________________________ preliminary confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
2) connect all analog grounds to a separate solid copper plane, which connects to the gnd pin of the MAX1987/max1988. this includes the v cc bypass capacitor, ref bypass capacitor, compen- sation (ccv) components, and the resistive- dividers connected to ilim and pos/neg. 3) keep the power traces and load connections short. this is essential for high efficiency. the use of thick copper pc boards (2oz vs. 1oz) can enhance full- load efficiency by 1% or more. correctly routing pc board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m ? of excess trace resistance c auses a measurable efficiency penalty. 4) keep the high-current gate-driver traces (dl_, dh_, lx_, and bst_) short and wide to minimize trace resistance and inductance. this is essential for high-power mosfets that require low-impedance gate drivers to avoid shoot-through currents. 5) c_p, c_n, oain+, and oain- connections for cur- rent limiting and voltage positioning must be made using kelvin sense connections to guarantee the current-sense accuracy. 6) when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. 7) route high-speed switching nodes away from sen- sitive analog areas (ref, ccv, cci, fb, c_p, c_n, etc.). make all pin-strap control input connections ( shdn , ilim, b0 to b2, s0 to s2, ton) to analog ground or v cc rather than power ground or v dd . layout procedure 1) place the power components first, with ground ter- minals adjacent (low-side mosfet source, c in , c out , and d1 anode). if possible, make all these connections on the top layer with wide, copper- filled areas. 2) mount the controller ic adjacent to the low-side mosfet. the dlm and dls gate traces must be short and wide (50mils to 100mils wide if the mosfet is 1in from the controller ic). 3) group the gate-drive components (bst_ diodes and capacitors, v dd bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as shown in figures 1 and 13. this diagram can be viewed as having three separate ground planes: input/output ground, where all the high-power com- ponents go; the power ground plane, where the pgnd pin and v dd bypass capacitor go; and the analog ground plane where sensitive analog com- ponents, the gnd pin, and v cc bypass capacitor go. the gnd plane must meet the pgnd plane only at a single point directly beneath the ic. the respec- tive ground planes should connect to the high- power output ground with a short metal trace from pgnd to the source of the low-side mosfet (the MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies ______________________________________________________________________________________ 41 b 1.4v 1.4v a a. conventional converter (50mv/div) b. voltage-positioned output (50mv/div) voltage positioning the output figure 11. voltage positioning the output v out esr voltage step (i step x r esr ) capacitive soar (dv/dt = i out /c out ) recovery capacitive sag (dv/dt = i out /c out ) i load figure 12. transient response regions confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
MAX1987/max1988 middle of the star ground). this point must also be very close to the output capacitor ground terminal. 5) connect the output power planes (v core and sys- tem ground planes) directly to the output filter capacitor positive and negative terminals with multi- ple vias. place the entire dc-dc converter circuit as close to the cpu as is practical. chip information transistor count: 9559 process: bicmos dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 42 ______________________________________________________________________________________ preliminary 5v bias supply input output active voltage positioning imvp-iv cpu main phase main i sense secondary i sense MAX1987 max1988 secondary phase typical operating circuit confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies ______________________________________________________________________________________ 43 preliminary via to analog ground vias to power ground power ground (2nd layer) power ground (2nd layer) connect the exposed pad to analog gnd connect gnd and pgnd to the controller at one point only as shown place controller on back side when possible, using the ground plane to shield the ic from emi main phase inductor power ground output secondary phase input cpu kelvin sense vias under the sense resistor (refer to the evaluation kit) c out c in c in c in c in c in c in c out c out c out c out c out inductor r sense r sense MAX1987/max1988 figure 13. pc board layout example confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies 44 ______________________________________________________________________________________ preliminary 32, 44, 48l qfn .eps proprietary information approval title: document control no. 21-0144 package outline 32, 44, 48l qfn thin, 7x7x0.8 mm 1 a rev. 2 e l e l a1 a a2 e/2 e d/2 d detail a d2/2 d2 b l k e2/2 e2 (ne-1) x e (nd-1) x e e c l c l c l c l k confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary MAX1987/max1988 dual-phase, quick-pwm controllers for imvp-iv cpu core power supplies maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 45 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) proprietary information document control no. approval title: a rev. 2 2 exposed pad variations 21-0144 package outline 32, 44, 48l qfn thin, 7x7x0.8 mm common dimensions ** note: t4877-1 is a custom 48l pkg. with 4 leads depopulated. total number of leads are 44. confidential information restricted to intel imvp licensees www.datasheet.co.kr datasheet pdf - http://www..net/

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